pwm.vhd

Pulse width modulation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pwm is
    Port ( din : buffer std_logic_vector(3 downto 0);
           dout : out std_logic;
           clk : in std_logic;
           reset : buffer bit;
            a : out bit;
			b : OUT bit;
			c : OUT bit;
			d : OUT bit;
			e : OUT bit;
			f : OUT bit
           );
end pwm;

architecture Behavioral of pwm is

signal count: std_logic_vector(13 downto 0);	  -- count is used to reduce the system frequency
signal cnt: std_logic_vector(3 downto 0);	  
signal s_clk: std_logic;	  
signal temp: std_logic_vector(3 downto 0):="0000";	  

begin		 

--U1:process(reset,clk)
--begin
--if (reset = '1') then
--    count <= (others => '0'); 
--elsif (clk'event and clk = '1') then
--    if (count = "0101111010000") then     -- counter has been set to divide the frequency by 65K
--		count <= (others => '0');
--    	s_clk<='0';
--	else
--		count <= count + '1';
--     	s_clk<='1';
--	end if;
--end if;
--end process;

U2:process(reset,clk)
begin
if (reset = '1') then
    cnt <= (others => '0'); 
elsif (clk'event and clk = '1') then
    if (cnt >= "1111") then     
		cnt <= (others => '0');
		dout<='1';
    else
		cnt <= cnt + '1';
    	if cnt >= temp then
			dout<='0';
		else
			dout<='1';
		end if;
    end if;
end if;
end process;

temp<=din;
din<="0010";

	d <= '1';--green
	a <= '1';--red
	
	c <= '0';--green
	b <= '1';--red
		
--	e <= '1';--green
	f <= '0';--red
 
end Behavioral;