clk_div.vhd

Clock division document

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library altera;
use altera.altera_syn_attributes.all;

entity clk_div is
    Port ( clk : in std_logic;
           reset : buffer bit
          );
end clk_div;

architecture Behavioral of clk_div is

signal count: std_logic_vector(20 downto 0);	  -- count is used to reduce the system frequency
signal cnt: std_logic_vector(3 downto 0);	  
signal s_clk: std_logic;	  
 
begin		 

U1:process(reset,clk)
begin
if (reset = '1') then
    count <= (others => '0'); 
elsif (clk'event and clk = '1') then
    if (count = "1010") then     -- counter has been set to divide the frequency by 65K
		count <= (others => '0');
    	s_clk<='0';
	else
		count <= count + '1';
     	s_clk<='1';
	end if;
end if;
end process;

end Behavioral;