tap.v

jtag TAP控制状态机代码 verilog VHDL

//  D:\DOWNLOADS\JTAG\DESIGN\TAP\TAP.v
//  Verilog created by Xilinx's StateCAD 5.03
//  Fri Nov 24 17:40:19 2006

//  This Verilog code (OVI compliant) was generated using: 
//  binary encoded state assignment with structured code format.
//  Minimization is enabled,  implied else is enabled, 
//  and outputs are speed optimized.

`timescale 1s/1s

module tap(CLK,TMS,TRST);

	input CLK;
	input TMS,TRST;
	reg [3:0] sreg;
	reg [3:0] next_sreg;

	`define CAPTURE_DR 4'b0000
	`define CAPTURE_IR 4'b0001
	`define EXIT1_DR 4'b0010
	`define EXIT1_IR 4'b0011
	`define EXIT2_DR 4'b0100
	`define EXIT2_IR 4'b0101
	`define PAUSE_DR 4'b0110
	`define PAUSE_IR 4'b0111
	`define RUN_TEST_IDLE 4'b1000
	`define SELECT_DR_SCAN 4'b1001
	`define SELECT_IR_SCAN 4'b1010
	`define SHIFT_DR 4'b1011
	`define SHIFT_IR 4'b1100
	`define TEST_LOGIC_RESET 4'b1101
	`define UPDATE_DR 4'b1110
	`define UPDATE_IR 4'b1111


	always @(posedge CLK or negedge TRST)
	begin
		if ( ~TRST ) begin
			sreg=`TEST_LOGIC_RESET;
		end else
		begin
			sreg = next_sreg;
		end
	end

	always @ (sreg or TMS)
	begin

		next_sreg=`CAPTURE_DR;

		case (sreg)
			`CAPTURE_DR : begin
				if ( TMS ) begin
					next_sreg=`EXIT1_DR;
				end
				if ( ~TMS ) begin
					next_sreg=`SHIFT_DR;
				end
			end
			`CAPTURE_IR : begin
				if ( TMS ) begin
					next_sreg=`EXIT1_IR;
				end
				if ( ~TMS ) begin
					next_sreg=`SHIFT_IR;
				end
			end
			`EXIT1_DR : begin
				if ( TMS ) begin
					next_sreg=`UPDATE_DR;
				end
				if ( ~TMS ) begin
					next_sreg=`PAUSE_DR;
				end
			end
			`EXIT1_IR : begin
				if ( ~TMS ) begin
					next_sreg=`PAUSE_IR;
				end
				if ( TMS ) begin
					next_sreg=`UPDATE_IR;
				end
			end
			`EXIT2_DR : begin
				if ( ~TMS ) begin
					next_sreg=`SHIFT_DR;
				end
				if ( TMS ) begin
					next_sreg=`UPDATE_DR;
				end
			end
			`EXIT2_IR : begin
				if ( TMS ) begin
					next_sreg=`UPDATE_IR;
				end
				if ( ~TMS ) begin
					next_sreg=`SHIFT_IR;
				end
			end
			`PAUSE_DR : begin
				if ( ~TMS ) begin
					next_sreg=`PAUSE_DR;
				end
				if ( TMS ) begin
					next_sreg=`EXIT2_DR;
				end
			end
			`PAUSE_IR : begin
				if ( TMS ) begin
					next_sreg=`EXIT2_IR;
				end
				if ( ~TMS ) begin
					next_sreg=`PAUSE_IR;
				end
			end
			`RUN_TEST_IDLE : begin
				if ( TMS ) begin
					next_sreg=`SELECT_DR_SCAN;
				end
				if ( ~TMS ) begin
					next_sreg=`RUN_TEST_IDLE;
				end
			end
			`SELECT_DR_SCAN : begin
				if ( TMS ) begin
					next_sreg=`SELECT_IR_SCAN;
				end
				if ( ~TMS ) begin
					next_sreg=`CAPTURE_DR;
				end
			end
			`SELECT_IR_SCAN : begin
				if ( TMS ) begin
					next_sreg=`TEST_LOGIC_RESET;
				end
				if ( ~TMS ) begin
					next_sreg=`CAPTURE_IR;
				end
			end
			`SHIFT_DR : begin
				if ( ~TMS ) begin
					next_sreg=`SHIFT_DR;
				end
				if ( TMS ) begin
					next_sreg=`EXIT1_DR;
				end
			end
			`SHIFT_IR : begin
				if ( TMS ) begin
					next_sreg=`EXIT1_IR;
				end
				if ( ~TMS ) begin
					next_sreg=`SHIFT_IR;
				end
			end
			`TEST_LOGIC_RESET : begin
				if ( ~TMS ) begin
					next_sreg=`RUN_TEST_IDLE;
				end
				if ( TMS ) begin
					next_sreg=`TEST_LOGIC_RESET;
				end
			end
			`UPDATE_DR : begin
				if ( ~TMS ) begin
					next_sreg=`RUN_TEST_IDLE;
				end
				if ( TMS ) begin
					next_sreg=`SELECT_DR_SCAN;
				end
			end
			`UPDATE_IR : begin
				if ( ~TMS ) begin
					next_sreg=`RUN_TEST_IDLE;
				end
				if ( TMS ) begin
					next_sreg=`SELECT_DR_SCAN;
				end
			end
		endcase
	end
endmodule