sst.vhd

数字电子钟设计

library ieee;
use ieee.std_logic_1164.all;
entity sst is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,q1k:out std_logic);
end sst;
architecture sss_arc of sst is
begin
process(clk)
begin
if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;

if  m1="0101" and m0="1001" and s1="0101" and s0="1001" then
q1k<='1';
else
q1k<='0';
end if;
end if;
end process;
end sss_arc;