mian.rpt

数字电子钟设计

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC24 co
        | +--------------- LC22 sec00
        | | +------------- LC21 sec01
        | | | +----------- LC19 sec02
        | | | | +--------- LC18 sec03
        | | | | | +------- LC25 sec10
        | | | | | | +----- LC17 sec11
        | | | | | | | +--- LC20 sec12
        | | | | | | | | +- LC23 sec13
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> * - - - - - - - - | - * | <-- co
LC22 -> * * * * * * * * * | - * | <-- sec00
LC21 -> * * * * * * * * * | - * | <-- sec01
LC19 -> * * - * * * * * * | - * | <-- sec02
LC18 -> * * * * * * * * * | - * | <-- sec03
LC25 -> * - - - * * * * * | - * | <-- sec10
LC17 -> * - - - * * * * * | - * | <-- sec11
LC20 -> * - - - * * * * * | - * | <-- sec12
LC23 -> * - - - * * * * * | - * | <-- sec13

Pin
43   -> - - - - - - - - - | - - | <-- clk
4    -> * * * * * * * * * | - * | <-- clr


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        c:\max2work\shuzi\mian.rpt
mian

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;

-- Node name is 'co' = ':11' 
-- Equation name is 'co', type is output 
 co      = DFFE( _EQ001 $  VCC, GLOBAL( clk),  VCC,  VCC, !clr);
  _EQ001 =  sec03 &  sec12 &  _X001 &  _X002
         #  sec03 &  sec13 &  _X001
         # !co &  _X003;
  _X001  = EXP(!sec00 & !sec01 & !sec02);
  _X002  = EXP(!sec10 & !sec11);
  _X003  = EXP( sec03 &  sec10 & !sec11 &  sec12 & !sec13);

-- Node name is 'sec00' = 'cnt00' 
-- Equation name is 'sec00', location is LC022, type is output.
 sec00   = DFFE( _EQ002 $ !sec03, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ002 = !sec00 & !sec01 & !sec02 &  sec03
         #  sec00 & !sec03;

-- Node name is 'sec01' = 'cnt01' 
-- Equation name is 'sec01', location is LC021, type is output.
 sec01   = DFFE( _EQ003 $ !sec03, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ003 =  sec00 &  sec01 & !sec03
         # !sec00 & !sec01 & !sec03;

-- Node name is 'sec02' = 'cnt02' 
-- Equation name is 'sec02', location is LC019, type is output.
 sec02   = DFFE( _EQ004 $ !sec03, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ004 =  sec00 &  sec01 &  sec02 & !sec03
         # !sec00 & !sec02 & !sec03
         # !sec01 & !sec02 & !sec03;

-- Node name is 'sec03' = 'cnt03' 
-- Equation name is 'sec03', location is LC018, type is output.
 sec03   = TFFE(!_EQ005, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ005 = !sec00 & !sec01 & !sec02 &  sec03 &  sec10 & !sec11 &  sec12 & 
             !sec13
         # !sec00 & !sec01 & !sec02 &  sec03 &  _X004
         # !sec03 &  _X004;
  _X004  = EXP( sec00 &  sec01 &  sec02);

-- Node name is 'sec10' = 'cnt10' 
-- Equation name is 'sec10', location is LC025, type is output.
 sec10   = TFFE(!_EQ006, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ006 = !sec10 &  sec11 &  sec12
         # !sec00 & !sec01 & !sec02
         # !sec10 &  sec13
         # !sec03;

-- Node name is 'sec11' = 'cnt11' 
-- Equation name is 'sec11', location is LC017, type is output.
 sec11   = DFFE( _EQ007 $  GND, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ007 =  sec03 &  sec10 & !sec11 & !sec12 & !sec13 &  _X001
         # !sec10 &  sec11 & !sec12 & !sec13
         # !sec00 & !sec01 & !sec02 &  sec11
         # !sec03 &  sec11;
  _X001  = EXP(!sec00 & !sec01 & !sec02);

-- Node name is 'sec12' = 'cnt12' 
-- Equation name is 'sec12', location is LC020, type is output.
 sec12   = DFFE( _EQ008 $  GND, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ008 =  sec03 &  sec10 &  sec11 & !sec12 & !sec13 &  _X001
         # !sec10 & !sec11 &  sec12 & !sec13
         # !sec00 & !sec01 & !sec02 &  sec12
         # !sec03 &  sec12;
  _X001  = EXP(!sec00 & !sec01 & !sec02);

-- Node name is 'sec13' = 'cnt13' 
-- Equation name is 'sec13', location is LC023, type is output.
 sec13   = TFFE(!_EQ009, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ009 =  sec12 & !sec13 &  _X002
         # !sec00 & !sec01 & !sec02
         # !sec13 &  _X005
         # !sec03;
  _X002  = EXP(!sec10 & !sec11);
  _X005  = EXP( sec10 &  sec11 &  sec12);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                 c:\max2work\shuzi\mian.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,378K