minute.rpt

数字电子钟设计

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC24 co
        | +--------------- LC22 min00
        | | +------------- LC21 min01
        | | | +----------- LC19 min02
        | | | | +--------- LC18 min03
        | | | | | +------- LC25 min10
        | | | | | | +----- LC17 min11
        | | | | | | | +--- LC20 min12
        | | | | | | | | +- LC23 min13
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> * - - - - - - - - | - * | <-- co
LC22 -> * * * * * * * * * | - * | <-- min00
LC21 -> * * * * * * * * * | - * | <-- min01
LC19 -> * * - * * * * * * | - * | <-- min02
LC18 -> * * * * * * * * * | - * | <-- min03
LC25 -> * - - - - * * * - | - * | <-- min10
LC17 -> * - - - - * * * - | - * | <-- min11
LC20 -> * - - - - * * * - | - * | <-- min12
LC23 -> * - - - - * * * * | - * | <-- min13

Pin
43   -> - - - - - - - - - | - - | <-- clk
4    -> * * * * * * * * * | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\max2work\shuzi\minute.rpt
minute

** EQUATIONS **

clk      : INPUT;
en       : INPUT;

-- Node name is 'co' = ':11' 
-- Equation name is 'co', type is output 
 co      = DFFE( _EQ001 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  en & !min00 & !min01 & !min02 &  min03 &  min10 & !min11 &  min12 & 
             !min13
         #  co & !min00 & !min01 & !min02
         #  co & !min10 & !min11 & !min13
         #  co & !min12 & !min13
         #  co &  _X001;
  _X001  = EXP( en &  min03);

-- Node name is 'min00' = 'cnt00' 
-- Equation name is 'min00', location is LC022, type is output.
 min00   = DFFE( _EQ002 $ !en, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  en & !min00 & !min01 & !min02
         #  en & !min00 & !min03
         # !en & !min00;

-- Node name is 'min01' = 'cnt01' 
-- Equation name is 'min01', location is LC021, type is output.
 min01   = TFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  en &  min00 & !min01 & !min03
         #  en &  min00 &  min01
         #  en &  min01 &  min03;

-- Node name is 'min02' = 'cnt02' 
-- Equation name is 'min02', location is LC019, type is output.
 min02   = TFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  en &  min00 &  min01 & !min02 & !min03
         #  en &  min00 &  min01 &  min02
         #  en &  min02 &  min03;

-- Node name is 'min03' = 'cnt03' 
-- Equation name is 'min03', location is LC018, type is output.
 min03   = TFFE(!_EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !min00 & !min01 & !min02 &  min03 &  _X002
         # !min03 &  _X002
         # !en;
  _X002  = EXP( min00 &  min01 &  min02);

-- Node name is 'min10' = 'cnt10' 
-- Equation name is 'min10', location is LC025, type is output.
 min10   = TFFE(!_EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !min10 &  min11 &  min12
         # !min00 & !min01 & !min02
         # !min10 &  min13
         # !min03
         # !en;

-- Node name is 'min11' = 'cnt11' 
-- Equation name is 'min11', location is LC017, type is output.
 min11   = TFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  en &  min03 &  min10 & !min11 & !min12 & !min13 &  _X003
         #  en &  min03 &  min10 &  min11 &  _X003
         #  en &  min03 &  min11 &  min12 &  _X003
         #  en &  min03 &  min11 &  min13 &  _X003;
  _X003  = EXP(!min00 & !min01 & !min02);

-- Node name is 'min12' = 'cnt12' 
-- Equation name is 'min12', location is LC020, type is output.
 min12   = DFFE( _EQ008 $  _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !min10 & !min11 &  min12 & !min13
         # !min00 & !min01 & !min02 &  min12
         # !min03 &  min12
         # !en &  min12;
  _EQ009 =  en &  min03 &  min10 &  min11 & !min12 & !min13 &  _X003;
  _X003  = EXP(!min00 & !min01 & !min02);

-- Node name is 'min13' = 'cnt13' 
-- Equation name is 'min13', location is LC023, type is output.
 min13   = TFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  en &  min03 &  min13 &  _X003;
  _X003  = EXP(!min00 & !min01 & !min02);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                               c:\max2work\shuzi\minute.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,457K