fenp.rpt

数字电子钟设计

! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                 d:\clock\fenp.rpt
fenp

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC17 cp1hz
        | +--------------------- LC18 cp500
        | | +------------------- LC27 |7490:10|QB
        | | | +----------------- LC26 |7490:10|QC
        | | | | +--------------- LC25 |7490:10|QD
        | | | | | +------------- LC24 |7490:11|QA
        | | | | | | +----------- LC23 |7490:11|QB
        | | | | | | | +--------- LC22 |7490:11|QC
        | | | | | | | | +------- LC21 |7490:11|QD
        | | | | | | | | | +----- LC20 |7490:12|QA
        | | | | | | | | | | +--- LC19 |7490:12|QB
        | | | | | | | | | | | +- LC28 |7490:12|QC
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - - - - - - - - - - * - | - * | <-- cp1hz
LC18 -> - * * * * - - - - - - - | - * | <-- cp500
LC27 -> - - * * * - - - - - - - | - * | <-- |7490:10|QB
LC26 -> - - - * * - - - - - - - | - * | <-- |7490:10|QC
LC25 -> - - * - - * - - - - - - | - * | <-- |7490:10|QD
LC24 -> - - - - - * * * * - - - | - * | <-- |7490:11|QA
LC23 -> - - - - - - * * * - - - | - * | <-- |7490:11|QB
LC22 -> - - - - - - - * * - - - | - * | <-- |7490:11|QC
LC21 -> - - - - - - * - - * - - | - * | <-- |7490:11|QD
LC20 -> * - - - - - - - - * * * | - * | <-- |7490:12|QA
LC19 -> * - - - - - - - - - * * | - * | <-- |7490:12|QB
LC28 -> * - - - - - - - - - - * | - * | <-- |7490:12|QC

Pin
4    -> - * - - - - - - - - - - | - * | <-- clk1k


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\clock\fenp.rpt
fenp

** EQUATIONS **

clk1k    : INPUT;

-- Node name is 'cp1hz' = '|7490:12|QD' 
-- Equation name is 'cp1hz', type is output 
 cp1hz   = DFFE( _EQ001 $  GND, !_LC020,  VCC,  VCC,  VCC);
  _EQ001 =  _LC019 &  _LC028;

-- Node name is 'cp500' = '|7490:10|QA' 
-- Equation name is 'cp500', type is output 
 cp500   = TFFE( VCC, !clk1k,  VCC,  VCC,  VCC);

-- Node name is '|7490:10|:11' = '|7490:10|QB' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( _EQ002 $  GND, !cp500,  VCC,  VCC,  VCC);
  _EQ002 = !_LC025 & !_LC027;

-- Node name is '|7490:10|:14' = '|7490:10|QC' 
-- Equation name is '_LC026', type is buried 
_LC026   = TFFE( _LC027, !cp500,  VCC,  VCC,  VCC);

-- Node name is '|7490:10|:19' = '|7490:10|QD' 
-- Equation name is '_LC025', type is buried 
_LC025   = DFFE( _EQ003 $  GND, !cp500,  VCC,  VCC,  VCC);
  _EQ003 =  _LC026 &  _LC027;

-- Node name is '|7490:11|:7' = '|7490:11|QA' 
-- Equation name is '_LC024', type is buried 
_LC024   = TFFE( VCC, !_LC025,  VCC,  VCC,  VCC);

-- Node name is '|7490:11|:11' = '|7490:11|QB' 
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( _EQ004 $  GND, !_LC024,  VCC,  VCC,  VCC);
  _EQ004 = !_LC021 & !_LC023;

-- Node name is '|7490:11|:14' = '|7490:11|QC' 
-- Equation name is '_LC022', type is buried 
_LC022   = TFFE( _LC023, !_LC024,  VCC,  VCC,  VCC);

-- Node name is '|7490:11|:19' = '|7490:11|QD' 
-- Equation name is '_LC021', type is buried 
_LC021   = DFFE( _EQ005 $  GND, !_LC024,  VCC,  VCC,  VCC);
  _EQ005 =  _LC022 &  _LC023;

-- Node name is '|7490:12|:7' = '|7490:12|QA' 
-- Equation name is '_LC020', type is buried 
_LC020   = TFFE( VCC, !_LC021,  VCC,  VCC,  VCC);

-- Node name is '|7490:12|:11' = '|7490:12|QB' 
-- Equation name is '_LC019', type is buried 
_LC019   = DFFE( _EQ006 $  GND, !_LC020,  VCC,  VCC,  VCC);
  _EQ006 = !cp1hz & !_LC019;

-- Node name is '|7490:12|:14' = '|7490:12|QC' 
-- Equation name is '_LC028', type is buried 
_LC028   = TFFE( _LC019, !_LC020,  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          d:\clock\fenp.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,636K