shuzi.rpt

数字电子钟设计

_LC7_C10 = LCELL( _EQ040);
  _EQ040 = !_LC5_C11 &  _LC8_C11;

-- Node name is '|MIAN:9|:207' 
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = LCELL( _EQ041);
  _EQ041 = !_LC4_C8 &  _LC4_C10 &  _LC8_C8
         # !_LC2_C6 &  _LC4_C10 &  _LC8_C8
         #  _LC2_C6 &  _LC4_C8 & !_LC4_C10 &  _LC8_C8;

-- Node name is '|MIAN:9|:216' 
-- Equation name is '_LC2_C8', type is buried 
_LC2_C8  = LCELL( _EQ042);
  _EQ042 = !_LC2_C6 &  _LC4_C8 &  _LC8_C8
         #  _LC2_C6 & !_LC4_C8 &  _LC8_C8;

-- Node name is '|MINUTE:32|:16' = '|MINUTE:32|cnt00' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = DFFE( _EQ043,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ043 = !_LC2_C11 &  _LC3_C16 &  _LC6_C6
         #  _LC2_C17 &  _LC6_C6
         #  _LC2_C11 & !_LC6_C6;

-- Node name is '|MINUTE:32|:15' = '|MINUTE:32|cnt01' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = DFFE( _EQ044,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ044 = !_LC2_C11 &  _LC2_C14 &  _LC2_C16
         #  _LC2_C11 & !_LC2_C14 &  _LC2_C16
         #  _LC2_C14 & !_LC6_C6;

-- Node name is '|MINUTE:32|:14' = '|MINUTE:32|cnt02' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = DFFE( _EQ045,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ045 =  _LC2_C16 & !_LC4_C16 &  _LC5_C16
         #  _LC2_C16 &  _LC4_C16 & !_LC5_C16
         #  _LC5_C16 & !_LC6_C6;

-- Node name is '|MINUTE:32|:13' = '|MINUTE:32|cnt03' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( _EQ046,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ046 =  _LC6_C6 &  _LC6_C16
         #  _LC2_C17 &  _LC6_C6
         #  _LC1_C16 & !_LC6_C6;

-- Node name is '|MINUTE:32|:20' = '|MINUTE:32|cnt10' 
-- Equation name is '_LC8_C17', type is buried 
_LC8_C17 = DFFE( _EQ047,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ047 =  _LC5_C17 &  _LC6_C6
         # !_LC6_C6 &  _LC8_C17
         #  _LC3_C16 &  _LC8_C17;

-- Node name is '|MINUTE:32|:19' = '|MINUTE:32|cnt11' 
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = DFFE( _EQ048,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ048 = !_LC2_C17 &  _LC6_C6 &  _LC7_C17
         # !_LC6_C6 &  _LC6_C17;

-- Node name is '|MINUTE:32|:18' = '|MINUTE:32|cnt12' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = DFFE( _EQ049,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ049 =  _LC4_C20 &  _LC6_C6
         #  _LC2_C17 &  _LC6_C6
         #  _LC1_C20 & !_LC6_C6;

-- Node name is '|MINUTE:32|:17' = '|MINUTE:32|cnt13' 
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = DFFE( _EQ050,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ050 =  _LC2_C20 & !_LC6_C6
         #  _LC2_C20 &  _LC3_C16;

-- Node name is '|MINUTE:32|LPM_ADD_SUB:80|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = LCELL( _EQ051);
  _EQ051 =  _LC2_C11 &  _LC2_C14;

-- Node name is '|MINUTE:32|LPM_ADD_SUB:107|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ052);
  _EQ052 =  _LC6_C17 &  _LC8_C17;

-- Node name is '|MINUTE:32|:11' 
-- Equation name is '_LC3_C6', type is buried 
_LC3_C6  = DFFE( _EQ053,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ053 =  _LC2_C17 &  _LC6_C6
         #  _LC1_C6 &  _LC3_C6;

-- Node name is '|MINUTE:32|~56~1' 
-- Equation name is '_LC1_C17', type is buried 
-- synthesized logic cell 
_LC1_C17 = LCELL( _EQ054);
  _EQ054 =  _LC1_C16 &  _LC1_C20 & !_LC2_C20 &  _LC8_C17;

-- Node name is '|MINUTE:32|:56' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ055);
  _EQ055 =  _LC1_C17 & !_LC6_C17 &  _LC8_C16;

-- Node name is '|MINUTE:32|:57' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ056);
  _EQ056 = !_LC1_C16
         #  _LC8_C16;

-- Node name is '|MINUTE:32|:59' 
-- Equation name is '_LC8_C16', type is buried 
_LC8_C16 = LCELL( _EQ057);
  _EQ057 = !_LC2_C11 & !_LC2_C14 & !_LC5_C16;

-- Node name is '|MINUTE:32|:88' 
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = LCELL( _EQ058);
  _EQ058 = !_LC1_C20 & !_LC2_C20
         # !_LC2_C20 & !_LC6_C17 & !_LC8_C17;

-- Node name is '|MINUTE:32|:173' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = LCELL( _EQ059);
  _EQ059 = !_LC1_C16 &  _LC4_C16 &  _LC5_C16
         #  _LC1_C16 & !_LC5_C16 &  _LC8_C16
         #  _LC1_C16 & !_LC4_C16 &  _LC8_C16;

-- Node name is '|MINUTE:32|~216~1' 
-- Equation name is '_LC4_C20', type is buried 
-- synthesized logic cell 
_LC4_C20 = LCELL( _EQ060);
  _EQ060 =  _LC1_C20 &  _LC3_C16
         #  _LC1_C20 & !_LC3_C20 &  _LC4_C17
         # !_LC1_C20 & !_LC3_C16 &  _LC3_C20 &  _LC4_C17;

-- Node name is '|MINUTE:32|:222' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = LCELL( _EQ061);
  _EQ061 =  _LC3_C16 &  _LC6_C17
         #  _LC4_C17 &  _LC6_C17 & !_LC8_C17
         # !_LC3_C16 &  _LC4_C17 & !_LC6_C17 &  _LC8_C17;

-- Node name is '|MINUTE:32|~247~1' 
-- Equation name is '_LC1_C6', type is buried 
-- synthesized logic cell 
_LC1_C6  = LCELL( _EQ062);
  _EQ062 =  _LC4_C17
         # !_LC6_C6
         #  _LC3_C16;

-- Node name is '|MINUTE:32|~260~1' 
-- Equation name is '_LC2_C16', type is buried 
-- synthesized logic cell 
_LC2_C16 = LCELL( _EQ063);
  _EQ063 = !_LC1_C16 & !_LC2_C17 &  _LC6_C6
         # !_LC2_C17 &  _LC6_C6 &  _LC8_C16;

-- Node name is '|MINUTE:32|~295~1' 
-- Equation name is '_LC5_C17', type is buried 
-- synthesized logic cell 
_LC5_C17 = LCELL( _EQ064);
  _EQ064 = !_LC3_C16 &  _LC4_C17 & !_LC8_C17
         #  _LC2_C17;

-- Node name is '|SST:4|:18' 
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = DFFE( _EQ065,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ065 = !_LC3_C11 &  _LC4_C11
         #  _LC1_C10 &  _LC3_C11 & !_LC6_C10;

-- Node name is '|SST:4|:20' 
-- Equation name is '_LC6_C11', type is buried 
_LC6_C11 = DFFE( _EQ066,  _LC8_C7,  VCC,  VCC,  VCC);
  _EQ066 =  _LC1_C10 &  _LC3_C11 &  _LC6_C10 &  _LC8_C9;

-- Node name is '|SST:4|~94~1' 
-- Equation name is '_LC3_C17', type is buried 
-- synthesized logic cell 
_LC3_C17 = LCELL( _EQ067);
  _EQ067 =  _LC1_C17 & !_LC2_C14 & !_LC5_C16 & !_LC6_C17;

-- Node name is '|SST:4|:94' 
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = LCELL( _EQ068);
  _EQ068 =  _LC2_C11 &  _LC3_C8 &  _LC3_C17;

-- Node name is ':6' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = LCELL( _EQ069);
  _EQ069 =  clk1k &  _LC6_C11 &  sb;

-- Node name is ':7' 
-- Equation name is '_LC1_C11', type is buried 
_LC1_C11 = LCELL( _EQ070);
  _EQ070 =  _LC7_C11
         #  _LC2_C1 &  _LC4_C11;

-- Node name is ':16' 
-- Equation name is '_LC8_C6', type is buried 
!_LC8_C6 = _LC8_C6~NOT;
_LC8_C6~NOT = LCELL( _EQ071);
  _EQ071 =  sa & !sb
         # !_LC3_C6 &  sa
         # !_LC5_C6 &  sa;

-- Node name is ':18' 
-- Equation name is '_LC6_C6', type is buried 
!_LC6_C6 = _LC6_C6~NOT;
_LC6_C6~NOT = LCELL( _EQ072);
  _EQ072 = !_LC5_C6 &  sb;



Project Information                                         c:\shuzi\shuzi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,008K