📄 shuzi.rpt
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that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - 21 OUTPUT 0 1 0 0 h00
58 - - C -- OUTPUT 0 1 0 0 h01
59 - - C -- OUTPUT 0 1 0 0 h02
60 - - C -- OUTPUT 0 1 0 0 h03
61 - - C -- OUTPUT 0 1 0 0 h10
62 - - C -- OUTPUT 0 1 0 0 h11
64 - - B -- OUTPUT 0 1 0 0 h12
65 - - B -- OUTPUT 0 1 0 0 h13
39 - - - 11 OUTPUT 0 1 0 0 m00
47 - - - 14 OUTPUT 0 1 0 0 m01
48 - - - 15 OUTPUT 0 1 0 0 m02
49 - - - 16 OUTPUT 0 1 0 0 m03
50 - - - 17 OUTPUT 0 1 0 0 m10
51 - - - 18 OUTPUT 0 1 0 0 m11
52 - - - 19 OUTPUT 0 1 0 0 m12
53 - - - 20 OUTPUT 0 1 0 0 m13
3 - - - 12 OUTPUT 0 1 0 0 sound
27 - - C -- OUTPUT 0 1 0 0 s00
28 - - C -- OUTPUT 0 1 0 0 s01
29 - - C -- OUTPUT 0 1 0 0 s02
30 - - C -- OUTPUT 0 1 0 0 s03
35 - - - 06 OUTPUT 0 1 0 0 s10
36 - - - 07 OUTPUT 0 1 0 0 s11
37 - - - 09 OUTPUT 0 1 0 0 s12
38 - - - 10 OUTPUT 0 1 0 0 s13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 01 DFFE + 0 0 0 4 |fenp:47|7490:10|QA (|fenp:47|7490:10|:7)
- 4 - C 01 DFFE 0 2 0 2 |fenp:47|7490:10|QB (|fenp:47|7490:10|:11)
- 3 - C 01 DFFE 0 2 0 1 |fenp:47|7490:10|QC (|fenp:47|7490:10|:14)
- 1 - C 01 DFFE 0 3 0 2 |fenp:47|7490:10|QD (|fenp:47|7490:10|:19)
- 4 - C 05 DFFE 0 1 0 3 |fenp:47|7490:11|QA (|fenp:47|7490:11|:7)
- 3 - C 05 DFFE 0 2 0 2 |fenp:47|7490:11|QB (|fenp:47|7490:11|:11)
- 2 - C 05 DFFE 0 2 0 1 |fenp:47|7490:11|QC (|fenp:47|7490:11|:14)
- 1 - C 05 DFFE 0 3 0 2 |fenp:47|7490:11|QD (|fenp:47|7490:11|:19)
- 3 - C 07 DFFE 0 1 0 3 |fenp:47|7490:12|QA (|fenp:47|7490:12|:7)
- 2 - C 07 DFFE 0 2 0 2 |fenp:47|7490:12|QB (|fenp:47|7490:12|:11)
- 1 - C 07 DFFE 0 2 0 1 |fenp:47|7490:12|QC (|fenp:47|7490:12|:14)
- 8 - C 07 DFFE 0 3 0 29 |fenp:47|7490:12|QD (|fenp:47|7490:12|:19)
- 8 - C 18 DFFE 0 1 1 1 |HOUR:33|cnt13 (|HOUR:33|:11)
- 7 - C 18 DFFE 0 1 1 1 |HOUR:33|cnt12 (|HOUR:33|:12)
- 1 - C 18 DFFE 0 3 1 1 |HOUR:33|cnt11 (|HOUR:33|:13)
- 2 - C 18 DFFE 0 1 1 1 |HOUR:33|cnt10 (|HOUR:33|:14)
- 4 - C 21 DFFE 0 4 1 6 |HOUR:33|cnt03 (|HOUR:33|:15)
- 5 - C 21 DFFE 0 4 1 4 |HOUR:33|cnt02 (|HOUR:33|:16)
- 7 - C 21 DFFE 0 4 1 5 |HOUR:33|cnt01 (|HOUR:33|:17)
- 1 - C 21 DFFE 0 4 1 5 |HOUR:33|cnt00 (|HOUR:33|:18)
- 3 - C 18 OR2 s 0 3 0 1 |HOUR:33|~52~1
- 6 - C 18 OR2 s 0 4 0 1 |HOUR:33|~52~2
- 2 - C 21 OR2 0 4 0 1 |HOUR:33|:53
- 8 - C 21 OR2 0 4 0 1 |HOUR:33|:123
- 6 - C 21 OR2 0 4 0 1 |HOUR:33|:132
- 3 - C 21 OR2 0 3 0 1 |HOUR:33|:141
- 5 - C 18 OR2 s 0 4 0 6 |HOUR:33|~178~1
- 4 - C 18 OR2 s 0 3 0 1 |HOUR:33|~207~1
- 8 - C 10 AND2 0 3 0 1 |MIAN:9|LPM_ADD_SUB:72|addcore:adder|:59
- 5 - C 06 DFFE 1 3 0 2 |MIAN:9|:11
- 3 - C 10 DFFE 1 2 1 2 |MIAN:9|cnt13 (|MIAN:9|:15)
- 4 - C 10 DFFE 1 4 1 3 |MIAN:9|cnt12 (|MIAN:9|:16)
- 4 - C 08 DFFE 1 4 1 4 |MIAN:9|cnt11 (|MIAN:9|:17)
- 2 - C 06 DFFE 1 4 1 4 |MIAN:9|cnt10 (|MIAN:9|:18)
- 6 - C 10 DFFE 1 4 1 4 |MIAN:9|cnt03 (|MIAN:9|:19)
- 5 - C 10 DFFE 1 4 1 2 |MIAN:9|cnt02 (|MIAN:9|:20)
- 2 - C 10 DFFE 1 4 1 3 |MIAN:9|cnt01 (|MIAN:9|:21)
- 1 - C 10 DFFE 1 3 1 7 |MIAN:9|cnt00 (|MIAN:9|:22)
- 3 - C 08 AND2 s 0 4 0 2 |MIAN:9|~48~1
- 5 - C 11 AND2 0 4 0 8 |MIAN:9|:48
- 8 - C 11 OR2 0 3 0 10 |MIAN:9|:49
- 8 - C 09 AND2 s 0 2 0 3 |MIAN:9|~51~1
- 1 - C 08 OR2 0 3 0 1 |MIAN:9|:83
- 8 - C 08 AND2 s 0 3 0 4 |MIAN:9|~150~1
- 4 - C 06 OR2 s 0 2 0 1 |MIAN:9|~154~1
- 7 - C 10 AND2 s 0 2 0 1 |MIAN:9|~174~1
- 5 - C 08 OR2 0 4 0 1 |MIAN:9|:207
- 2 - C 08 OR2 0 3 0 1 |MIAN:9|:216
- 4 - C 16 AND2 0 2 0 2 |MINUTE:32|LPM_ADD_SUB:80|addcore:adder|:55
- 3 - C 20 AND2 0 2 0 1 |MINUTE:32|LPM_ADD_SUB:107|addcore:adder|:55
- 3 - C 06 DFFE 0 4 0 1 |MINUTE:32|:11
- 1 - C 16 DFFE 0 4 1 4 |MINUTE:32|cnt03 (|MINUTE:32|:13)
- 5 - C 16 DFFE 0 4 1 3 |MINUTE:32|cnt02 (|MINUTE:32|:14)
- 2 - C 14 DFFE 0 4 1 3 |MINUTE:32|cnt01 (|MINUTE:32|:15)
- 2 - C 11 DFFE 0 4 1 4 |MINUTE:32|cnt00 (|MINUTE:32|:16)
- 2 - C 20 DFFE 0 3 1 2 |MINUTE:32|cnt13 (|MINUTE:32|:17)
- 1 - C 20 DFFE 0 4 1 3 |MINUTE:32|cnt12 (|MINUTE:32|:18)
- 6 - C 17 DFFE 0 4 1 5 |MINUTE:32|cnt11 (|MINUTE:32|:19)
- 8 - C 17 DFFE 0 4 1 5 |MINUTE:32|cnt10 (|MINUTE:32|:20)
- 1 - C 17 AND2 s 0 4 0 2 |MINUTE:32|~56~1
- 2 - C 17 AND2 0 3 0 7 |MINUTE:32|:56
- 3 - C 16 OR2 0 2 0 7 |MINUTE:32|:57
- 8 - C 16 AND2 0 3 0 4 |MINUTE:32|:59
- 4 - C 17 OR2 0 4 0 4 |MINUTE:32|:88
- 6 - C 16 OR2 0 4 0 1 |MINUTE:32|:173
- 4 - C 20 OR2 s 0 4 0 1 |MINUTE:32|~216~1
- 7 - C 17 OR2 0 4 0 1 |MINUTE:32|:222
- 1 - C 06 OR2 s 0 3 0 1 |MINUTE:32|~247~1
- 2 - C 16 OR2 s 0 4 0 2 |MINUTE:32|~260~1
- 5 - C 17 OR2 s 0 4 0 1 |MINUTE:32|~295~1
- 4 - C 11 DFFE 0 4 0 1 |SST:4|:18
- 6 - C 11 DFFE 0 5 0 1 |SST:4|:20
- 3 - C 17 AND2 s 0 4 0 1 |SST:4|~94~1
- 3 - C 11 AND2 0 3 0 2 |SST:4|:94
- 7 - C 11 AND2 2 1 0 1 :6
- 1 - C 11 OR2 0 3 1 0 :7
- 8 - C 06 OR2 ! 2 2 0 6 :16
- 6 - C 06 AND2 ! 1 1 0 11 :18
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 14/ 96( 14%) 19/ 48( 39%) 18/ 48( 37%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** CLOCK SIGNALS **
Type Fan-out Name
DFF 29 |fenp:47|7490:12|QD
DFF 5 |fenp:47|7490:10|QA
DFF 4 |fenp:47|7490:11|QA
DFF 4 |fenp:47|7490:12|QA
INPUT 2 clk1k
DFF 2 |fenp:47|7490:10|QD
DFF 2 |fenp:47|7490:11|QD
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 sc
Device-Specific Information: c:\shuzi\shuzi.rpt
shuzi
** EQUATIONS **
clk1k : INPUT;
sa : INPUT;
sb : INPUT;
sc : INPUT;
-- Node name is 'h00'
-- Equation name is 'h00', type is output
h00 = _LC1_C21;
-- Node name is 'h01'
-- Equation name is 'h01', type is output
h01 = _LC7_C21;
-- Node name is 'h02'
-- Equation name is 'h02', type is output
h02 = _LC5_C21;
-- Node name is 'h03'
-- Equation name is 'h03', type is output
h03 = _LC4_C21;
-- Node name is 'h10'
-- Equation name is 'h10', type is output
h10 = _LC2_C18;
-- Node name is 'h11'
-- Equation name is 'h11', type is output
h11 = _LC1_C18;
-- Node name is 'h12'
-- Equation name is 'h12', type is output
h12 = _LC7_C18;
-- Node name is 'h13'
-- Equation name is 'h13', type is output
h13 = _LC8_C18;
-- Node name is 'm00'
-- Equation name is 'm00', type is output
m00 = _LC2_C11;
-- Node name is 'm01'
-- Equation name is 'm01', type is output
m01 = _LC2_C14;
-- Node name is 'm02'
-- Equation name is 'm02', type is output
m02 = _LC5_C16;
-- Node name is 'm03'
-- Equation name is 'm03', type is output
m03 = _LC1_C16;
-- Node name is 'm10'
-- Equation name is 'm10', type is output
m10 = _LC8_C17;
-- Node name is 'm11'
-- Equation name is 'm11', type is output
m11 = _LC6_C17;
-- Node name is 'm12'
-- Equation name is 'm12', type is output
m12 = _LC1_C20;
-- Node name is 'm13'
-- Equation name is 'm13', type is output
m13 = _LC2_C20;
-- Node name is 'sound'
-- Equation name is 'sound', type is output
sound = _LC1_C11;
-- Node name is 's00'
-- Equation name is 's00', type is output
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