crc.vhd

编码实验Your use of Altera Corporation s design tools, logic functions and other software and tools, a

--实验6.2 
--4位CRC编码和校验

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CRC IS
PORT ( choice     : IN   STD_LOGIC;                     --控制位：为0时进行CRC编码；为1时进行CRC校验
       data_in    : IN   STD_LOGIC_VECTOR(3 DOWNTO 0);  --输入4位数据，对其进行CRC编码
       data_CRC   : OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);  --输出4位数据的CRC编码，7位
       data_check : IN   STD_LOGIC_VECTOR(6 DOWNTO 0);  --输入待验证的7位CRC码
                s : OUT  STD_LOGIC_VECTOR(2 DOWNTO 0)   --输出校验的结果值，指出哪位错误 
     );
END CRC;

ARCHITECTURE behav OF  CRC IS
BEGIN
  --求出余数
  PROCESS(choice,data_in,data_check)
    VARIABLE d_temp: STD_LOGIC_VECTOR(6 DOWNTO 0);
    VARIABLE reg_t : STD_LOGIC_VECTOR(2 DOWNTO 0);
    VARIABLE highest: STD_LOGIC; 
    BEGIN

      IF choice='0' 
      THEN d_temp := data_in(3 DOWNTO 0) & "000";
      ELSE d_temp := data_check;
      END IF;

      reg_t := d_temp(6 DOWNTO 4);
      
      FOR i in 3 downto 0 loop
      highest := reg_t(2);
      reg_t   := reg_t(1 DOWNTO 0) & d_temp(i);
      IF highest='1' THEN
        reg_t := reg_t XOR "011";
      END IF;
      end loop;
      
      --结果赋值
      IF choice='0' 
      THEN data_CRC <= data_in(3 DOWNTO 0) & reg_t(2 DOWNTO 0);
      ELSE s        <= reg_t;
      END IF;

    END PROCESS;
  
END behav;