crc.tan.qmsg

编码实验Your use of Altera Corporation s design tools, logic functions and other software and tools, a

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_CRC\[4\]\$latch " "Info: Node \"data_CRC\[4\]\$latch\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_CRC\[3\]\$latch " "Info: Node \"data_CRC\[3\]\$latch\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_CRC\[2\]\$latch " "Info: Node \"data_CRC\[2\]\$latch\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_CRC\[1\]\$latch " "Info: Node \"data_CRC\[1\]\$latch\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "data_CRC\[0\]\$latch " "Info: Node \"data_CRC\[0\]\$latch\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data_check\[4\] s\[2\] 13.699 ns Longest " "Info: Longest tpd from source pin \"data_check\[4\]\" to destination pin \"s\[2\]\" is 13.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns data_check\[4\] 1 PIN PIN_214 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 2; PIN Node = 'data_check\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_check[4] } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.017 ns) + CELL(0.590 ns) 8.082 ns reg_t~160 2 COMB LC_X24_Y20_N9 2 " "Info: 2: + IC(6.017 ns) + CELL(0.590 ns) = 8.082 ns; Loc. = LC_X24_Y20_N9; Fanout = 2; COMB Node = 'reg_t~160'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.607 ns" { data_check[4] reg_t~160 } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.014 ns) 9.096 ns s\[2\]\$latch 3 COMB LOOP LC_X24_Y20_N5 2 " "Info: 3: + IC(0.000 ns) + CELL(1.014 ns) = 9.096 ns; Loc. = LC_X24_Y20_N5; Fanout = 2; COMB LOOP Node = 's\[2\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "s\[2\]\$latch LC_X24_Y20_N5 " "Info: Loc. = LC_X24_Y20_N5; Node \"s\[2\]\$latch\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s[2]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s[2]$latch } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { reg_t~160 s[2]$latch } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.479 ns) + CELL(2.124 ns) 13.699 ns s\[2\] 4 PIN PIN_175 0 " "Info: 4: + IC(2.479 ns) + CELL(2.124 ns) = 13.699 ns; Loc. = PIN_175; Fanout = 0; PIN Node = 's\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.603 ns" { s[2]$latch s[2] } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.203 ns ( 37.98 % ) " "Info: Total cell delay = 5.203 ns ( 37.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.496 ns ( 62.02 % ) " "Info: Total interconnect delay = 8.496 ns ( 62.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.699 ns" { data_check[4] reg_t~160 s[2]$latch s[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.699 ns" { data_check[4] data_check[4]~out0 reg_t~160 s[2]$latch s[2] } { 0.000ns 0.000ns 6.017ns 0.000ns 2.479ns } { 0.000ns 1.475ns 0.590ns 1.014ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "choice data_CRC\[2\] 10.755 ns Shortest " "Info: Shortest tpd from source pin \"choice\" to destination pin \"data_CRC\[2\]\" is 10.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns choice 1 PIN PIN_12 20 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_12; Fanout = 20; PIN Node = 'choice'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { choice } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.834 ns) 7.303 ns data_CRC\[2\]\$latch 2 COMB LOOP LC_X1_Y7_N2 2 " "Info: 2: + IC(0.000 ns) + CELL(5.834 ns) = 7.303 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; COMB LOOP Node = 'data_CRC\[2\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "data_CRC\[2\]\$latch LC_X1_Y7_N2 " "Info: Loc. = LC_X1_Y7_N2; Node \"data_CRC\[2\]\$latch\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_CRC[2]$latch } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { data_CRC[2]$latch } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.834 ns" { choice data_CRC[2]$latch } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.328 ns) + CELL(2.124 ns) 10.755 ns data_CRC\[2\] 3 PIN PIN_43 0 " "Info: 3: + IC(1.328 ns) + CELL(2.124 ns) = 10.755 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'data_CRC\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.452 ns" { data_CRC[2]$latch data_CRC[2] } "NODE_NAME" } } { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.427 ns ( 87.65 % ) " "Info: Total cell delay = 9.427 ns ( 87.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.328 ns ( 12.35 % ) " "Info: Total interconnect delay = 1.328 ns ( 12.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.755 ns" { choice data_CRC[2]$latch data_CRC[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.755 ns" { choice choice~out0 data_CRC[2]$latch data_CRC[2] } { 0.000ns 0.000ns 0.000ns 1.328ns } { 0.000ns 1.469ns 5.834ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 22 14:49:26 2007 " "Info: Processing ended: Thu Mar 22 14:49:26 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}