crc.map.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L2 is d_temp~70
--operation mode is normal

A1L2 = choice & data_check[5] # !choice & (data_in[2]);


--A1L43 is reg_t~341
--operation mode is normal

A1L43 = A1L2 $ (choice & (data_check[6]) # !choice & data_in[3]);


--A1L3 is d_temp~71
--operation mode is normal

A1L3 = choice & data_check[3] # !choice & (data_in[0]);


--A1L53 is reg_t~342
--operation mode is normal

A1L53 = A1L43 $ A1L3 $ (choice & data_check[0]);


--data_CRC[0]$latch is data_CRC[0]$latch
--operation mode is normal

data_CRC[0]$latch = choice & (data_CRC[0]$latch) # !choice & A1L53;


--A1L4 is d_temp~72
--operation mode is normal

A1L4 = choice & data_check[1];


--A1L5 is d_temp~73
--operation mode is normal

A1L5 = choice & data_check[4] # !choice & (data_in[1]);


--A1L63 is reg_t~343
--operation mode is normal

A1L63 = A1L2 $ A1L3 $ A1L4 $ A1L5;


--data_CRC[1]$latch is data_CRC[1]$latch
--operation mode is normal

data_CRC[1]$latch = choice & (data_CRC[1]$latch) # !choice & A1L63;


--A1L73 is reg_t~344
--operation mode is normal

A1L73 = A1L43 $ A1L5 $ (choice & data_check[2]);


--data_CRC[2]$latch is data_CRC[2]$latch
--operation mode is normal

data_CRC[2]$latch = choice & (data_CRC[2]$latch) # !choice & A1L73;


--data_CRC[3]$latch is data_CRC[3]$latch
--operation mode is normal

data_CRC[3]$latch = choice & (data_CRC[3]$latch) # !choice & data_in[0];


--data_CRC[4]$latch is data_CRC[4]$latch
--operation mode is normal

data_CRC[4]$latch = choice & (data_CRC[4]$latch) # !choice & data_in[1];


--data_CRC[5]$latch is data_CRC[5]$latch
--operation mode is normal

data_CRC[5]$latch = choice & (data_CRC[5]$latch) # !choice & data_in[2];


--data_CRC[6]$latch is data_CRC[6]$latch
--operation mode is normal

data_CRC[6]$latch = choice & (data_CRC[6]$latch) # !choice & data_in[3];


--s[0]$latch is s[0]$latch
--operation mode is normal

s[0]$latch = choice & A1L53 # !choice & (s[0]$latch);


--s[1]$latch is s[1]$latch
--operation mode is normal

s[1]$latch = choice & A1L63 # !choice & (s[1]$latch);


--s[2]$latch is s[2]$latch
--operation mode is normal

s[2]$latch = choice & A1L73 # !choice & (s[2]$latch);


--choice is choice
--operation mode is input

choice = INPUT();


--data_check[0] is data_check[0]
--operation mode is input

data_check[0] = INPUT();


--data_in[3] is data_in[3]
--operation mode is input

data_in[3] = INPUT();


--data_check[6] is data_check[6]
--operation mode is input

data_check[6] = INPUT();


--data_check[5] is data_check[5]
--operation mode is input

data_check[5] = INPUT();


--data_in[2] is data_in[2]
--operation mode is input

data_in[2] = INPUT();


--data_check[3] is data_check[3]
--operation mode is input

data_check[3] = INPUT();


--data_in[0] is data_in[0]
--operation mode is input

data_in[0] = INPUT();


--data_check[1] is data_check[1]
--operation mode is input

data_check[1] = INPUT();


--data_check[4] is data_check[4]
--operation mode is input

data_check[4] = INPUT();


--data_in[1] is data_in[1]
--operation mode is input

data_in[1] = INPUT();


--data_check[2] is data_check[2]
--operation mode is input

data_check[2] = INPUT();


--data_CRC[0] is data_CRC[0]
--operation mode is output

data_CRC[0] = OUTPUT(data_CRC[0]$latch);


--data_CRC[1] is data_CRC[1]
--operation mode is output

data_CRC[1] = OUTPUT(data_CRC[1]$latch);


--data_CRC[2] is data_CRC[2]
--operation mode is output

data_CRC[2] = OUTPUT(data_CRC[2]$latch);


--data_CRC[3] is data_CRC[3]
--operation mode is output

data_CRC[3] = OUTPUT(data_CRC[3]$latch);


--data_CRC[4] is data_CRC[4]
--operation mode is output

data_CRC[4] = OUTPUT(data_CRC[4]$latch);


--data_CRC[5] is data_CRC[5]
--operation mode is output

data_CRC[5] = OUTPUT(data_CRC[5]$latch);


--data_CRC[6] is data_CRC[6]
--operation mode is output

data_CRC[6] = OUTPUT(data_CRC[6]$latch);


--s[0] is s[0]
--operation mode is output

s[0] = OUTPUT(s[0]$latch);


--s[1] is s[1]
--operation mode is output

s[1] = OUTPUT(s[1]$latch);


--s[2] is s[2]
--operation mode is output

s[2] = OUTPUT(s[2]$latch);