prev_cmp_led.fit.qmsg

Altera CycloneII EP2C8 的一些小试验程序.用的是V---.

{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Clk " "Warning: Node \"Clk\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[0\] " "Warning: Node \"LCD12864_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[1\] " "Warning: Node \"LCD12864_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[2\] " "Warning: Node \"LCD12864_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[3\] " "Warning: Node \"LCD12864_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[4\] " "Warning: Node \"LCD12864_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[5\] " "Warning: Node \"LCD12864_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[6\] " "Warning: Node \"LCD12864_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_D\[7\] " "Warning: Node \"LCD12864_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_D\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_E " "Warning: Node \"LCD12864_E\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_E" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_RS " "Warning: Node \"LCD12864_RS\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_RS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD12864_RW " "Warning: Node \"LCD12864_RW\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD12864_RW" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[0\] " "Warning: Node \"LCD1602_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[1\] " "Warning: Node \"LCD1602_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[2\] " "Warning: Node \"LCD1602_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[3\] " "Warning: Node \"LCD1602_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[4\] " "Warning: Node \"LCD1602_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[5\] " "Warning: Node \"LCD1602_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[6\] " "Warning: Node \"LCD1602_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_D\[7\] " "Warning: Node \"LCD1602_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_D\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_E " "Warning: Node \"LCD1602_E\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_E" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_RS " "Warning: Node \"LCD1602_RS\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_RS" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD1602_RW " "Warning: Node \"LCD1602_RW\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD1602_RW" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_12864_/RES " "Warning: Node \"LCD_12864_/RES\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_12864_/RES" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_12864_CS1 " "Warning: Node \"LCD_12864_CS1\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_12864_CS1" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_12864_CS2 " "Warning: Node \"LCD_12864_CS2\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_12864_CS2" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Rst_n " "Warning: Node \"Rst_n\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Rst_n" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[0\] " "Warning: Node \"Sev_Seg_Led_Data_n\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[1\] " "Warning: Node \"Sev_Seg_Led_Data_n\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[2\] " "Warning: Node \"Sev_Seg_Led_Data_n\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[3\] " "Warning: Node \"Sev_Seg_Led_Data_n\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[4\] " "Warning: Node \"Sev_Seg_Led_Data_n\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[5\] " "Warning: Node \"Sev_Seg_Led_Data_n\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[6\] " "Warning: Node \"Sev_Seg_Led_Data_n\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sev_Seg_Led_Data_n\[7\] " "Warning: Node \"Sev_Seg_Led_Data_n\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Data_n\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sw_n\[0\] " "Warning: Node \"Sw_n\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sw_n\[0\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sw_n\[1\] " "Warning: Node \"Sw_n\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sw_n\[1\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sw_n\[2\] " "Warning: Node \"Sw_n\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sw_n\[2\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Sw_n\[3\] " "Warning: Node \"Sw_n\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sw_n\[3\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "14 " "Warning: Found 14 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led_En_n 0 " "Info: Pin \"Led_En_n\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[0\] 0 " "Info: Pin \"Led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[1\] 0 " "Info: Pin \"Led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[2\] 0 " "Info: Pin \"Led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[3\] 0 " "Info: Pin \"Led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[4\] 0 " "Info: Pin \"Led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[5\] 0 " "Info: Pin \"Led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d!