fr_div.eqn

来自「DDS divider clock AHDL」· EQN 代码 · 共 57 行

--C1_sload_path[2] is lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] at LC3_1_A2
--operation mode is normal

C1_sload_path[2]_lut_out = C1L5 $ !C1_sload_path[2];
C1_sload_path[2] = DFFE(C1_sload_path[2]_lut_out, GLOBAL(fin_X_2), , , );


--C1_sload_path[1] is lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] at LC2_1_A2
--operation mode is arithmetic

C1_sload_path[1]_lut_out = C1_sload_path[1] $ C1L3;
C1_sload_path[1] = DFFE(C1_sload_path[1]_lut_out, GLOBAL(fin_X_2), , , );

--C1L5 is lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT at LC2_1_A2
--operation mode is arithmetic

C1L5 = CARRY(!C1L3 # !C1_sload_path[1]);


--C1_sload_path[0] is lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] at LC1_1_A2
--operation mode is qfbk_counter

C1_sload_path[0]_lut_out = !C1_sload_path[0];
C1_sload_path[0] = DFFE(C1_sload_path[0]_lut_out, GLOBAL(fin_X_2), , , );

--C1L3 is lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[0]~COUT at LC1_1_A2
--operation mode is qfbk_counter

C1L3 = CARRY(C1_sload_path[0]);


--rgF is rgF at LC3_2_D1
--operation mode is normal

rgF_lut_out = !rgF;
rgF = DFFE(rgF_lut_out, GLOBAL(fin_X_2), , , );


--fin_X_2 is fin_X_2 at LC3_3_D1
--operation mode is normal

fin_X_2 = rgF $ Fin;


--Fin is Fin at Pin_25
--operation mode is input

Fin = INPUT();


--Fout is Fout at Pin_6
--operation mode is output

Fout = OUTPUT(C1_sload_path[2]);