fr_div.csf.msg

DDS divider clock AHDL

{  "Info" "IFIT_FIT_ATTEMPT" "1 Tue Apr 28 2009 21:08:43 " "Started  fitting attempt 1 on Tue Apr 28 2009 at 21:08:43" {  } {  } 0 }
{  "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 }
{  "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.198 ns register register " "Estimated most critical path is register to register delay of 2.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\] 1 REG LAB_1_A2 " "1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(1.122 ns) 1.529 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|counter_cell\[1\]~COUT 2 COMB LAB_1_A2 " "2: + IC(0.246 ns) + CELL(1.122 ns) = 1.529 ns; Loc. = LAB_1_A2; COMB Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "1.368 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 765 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.669 ns) 2.198 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\] 3 REG LAB_1_A2 " "3: + IC(0.000 ns) + CELL(0.669 ns) = 2.198 ns; Loc. = LAB_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "0.669 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.952 ns " "Total cell delay = 1.952 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.246 ns " "Total interconnect delay = 0.246 ns" {  } {  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "2.198 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } }  } 0 }
{  "Info" "ITAN_SCC_LOOP" "2 " "Found combinatorial loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "fin_X_2 " "Node fin_X_2" {  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 20 1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "rgF " "Node rgF" {  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 17 1 0 } }  } 0}  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 20 1 0 } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 17 1 0 } }  } 0 }
{  "Warning" "WTDB_NO_CLOCKS" "" "Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "Fin " "Assuming node Fin is an undefined clock" {  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 12 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Fin register register lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\] lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\] 279.02 MHz Internal " "Clock Fin Internal fmax is restricted to 279.02 MHz between source register lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\] and destination register lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\]" { { "Info" "ITDB_CLOCK_RATE" "clock 3.584 ns " "fmax restricted to clock pin edge rate 3.584 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.753 ns + Longest register register " "+ Longest register to register delay is 1.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\] 1 REG LC2_1_A2 " "1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC2_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.670 ns) 1.084 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|counter_cell\[1\]~COUT 2 COMB LC2_1_A2 " "2: + IC(0.253 ns) + CELL(0.670 ns) = 1.084 ns; Loc. = LC2_1_A2; COMB Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "0.923 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 765 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.669 ns) 1.753 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\] 3 REG LC3_1_A2 " "3: + IC(0.000 ns) + CELL(0.669 ns) = 1.753 ns; Loc. = LC3_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "0.669 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns " "Total cell delay = 1.500 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.253 ns " "Total interconnect delay = 0.253 ns" {  } {  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "1.753 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "- Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin destination 9.543 ns + Shortest register " "+ Shortest clock path from clock Fin to destination register is 9.543 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns Fin 1 CLK Pin_25 " "1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_25; CLK Node = 'Fin'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { Fin } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 12 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.714 ns) 5.954 ns fin_X_2 2 COMB LOOP LC3_3_D1 " "2: + IC(0.000 ns) + CELL(4.714 ns) = 5.954 ns; Loc. = LC3_3_D1; COMB LOOP Node = 'fin_X_2'" { { "Info" "ITDB_PART_OF_SCC" "rgF LC3_2_D1 " "Loc. = LC3_2_D1; Node rgF" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { rgF } "NODE_NAME" } } }  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { rgF } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 17 1 0 } } { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "4.714 ns" { Fin fin_X_2 } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 20 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.589 ns) + CELL(0.000 ns) 9.543 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\] 3 REG LC3_1_A2 " "3: + IC(3.589 ns) + CELL(0.000 ns) = 9.543 ns; Loc. = LC3_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[2\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "3.589 ns" { fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.954 ns " "Total cell delay = 5.954 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.589 ns " "Total interconnect delay = 3.589 ns" {  } {  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin source 9.543 ns - Longest register " "- Longest clock path from clock Fin to source register is 9.543 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns Fin 1 CLK Pin_25 " "1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_25; CLK Node = 'Fin'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { Fin } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 12 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.714 ns) 5.954 ns fin_X_2 2 COMB LOOP LC3_3_D1 " "2: + IC(0.000 ns) + CELL(4.714 ns) = 5.954 ns; Loc. = LC3_3_D1; COMB LOOP Node = 'fin_X_2'" { { "Info" "ITDB_PART_OF_SCC" "rgF LC3_2_D1 " "Loc. = LC3_2_D1; Node rgF" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { rgF } "NODE_NAME" } } }  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { rgF } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 17 1 0 } } { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "4.714 ns" { Fin fin_X_2 } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 20 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.589 ns) + CELL(0.000 ns) 9.543 ns lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\] 3 REG LC2_1_A2 " "3: + IC(3.589 ns) + CELL(0.000 ns) = 9.543 ns; Loc. = LC2_1_A2; REG Node = 'lpm_counter:fv_rtl_0\|alt_synch_counter:wysi_counter\|sload_path\[1\]'" {  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "3.589 ns" { fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.954 ns " "Total cell delay = 5.954 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.589 ns " "Total interconnect delay = 3.589 ns" {  } {  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } }  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "+ Micro clock to output delay of source is 0.335 ns" {  } { { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "+ Micro setup delay of destination is 0.198 ns" {  } { { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "1.753 ns" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "9.543 ns" { Fin Fin~out0 fin_X_2 lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] } "NODE_NAME" } } }  } 0}  } { { "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" "" "" { Report "c:\\qdesigns\\fr_div\\db\\fr_div_bars_V1_cmp.qrpt" Compiler "fr_div" "bars" "V1" "c:\\qdesigns\\fr_div\\db\\fr_div.quartus_db" { Floorplan "" "" "" { lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] } "NODE_NAME" } } } { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 784 14 0 } }  } 0 }
{  "Info" "IDBC_ERROR_COUNT" "0 2 s s Full compilation fr_div successful was " "Design fr_div: Full compilation was successful. 0 errors, 2 warnings" {  } {  } 2 }