fr_div.csf.msg

DDS divider clock AHDL

{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:\\qdesigns\\fr_div\\fr_div.tdf 1 1 " "Found 1 design units and 1 entities in source file c:\\qdesigns\\fr_div\\fr_div.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 fr_div " "Found entity 1: fr_div" {  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "fr_div" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 10 1 0 } }  } 0}  } {  } 0 }
{  "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fv\[0\] data_in GND " "Reduced register fv\[0\] with stuck data_in port to stuck value GND" {  } { { "c:\\qdesigns\\fr_div\\fr_div.tdf" "" "" { Text "c:\\qdesigns\\fr_div\\fr_div.tdf" 16 3 0 } }  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf 1 1 " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Found entity 1: lpm_counter" {  } { { "C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" "lpm_counter" "" { Text "C:\\quartus\\libraries\\megafunctions\\lpm_counter.tdf" 212 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf 1 1 " "Found 1 design units and 1 entities in source file C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_counter " "Found entity 1: alt_synch_counter" {  } { { "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" "alt_synch_counter" "" { Text "C:\\quartus\\libraries\\megafunctions\\alt_synch_counter.tdf" 457 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Implemented 7 device resources" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Implemented 5 logic cells" {  } {  } 0}  } {  } 0 }
{  "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "fr_div EP20K30ETC144-1 " "Automatically selected device EP20K30ETC144-1 for design fr_div" {  } {  } 0 }
{  "Info" "IFIT_FIT_SIGNALPROBE_SMART_COMPILATION_OFF" "" "Smart compilation turned off -- SignalProbe information will not be saved" {  } {  } 0 }
{  "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "fin_X_2 automatically " "Promoted cell fin_X_2 to global signal automatically" {  } {  } 0 }