fr_div.csf.rpt

DDS divider clock AHDL

| 2            | 4    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 5    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 6    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 7    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 8    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 9    | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 10   | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| 2            | 11   | 80                     |  0 / 80 ( 0 % )   |  0 / 160 ( 0 % )       |
| Total        |      | 1760                   |  0 / 1760 ( 0 % ) |  0 / 3520 ( 0 % )      |
+--------------+------+------------------------+-------------------+------------------------+

+-----------------------------------------------------------------------------+
| ESB Column Interconnect                                                     |
+-----------------------------------------------------------------------------+
+-------+------------------------+-------------------+------------------------+
| Col.  | Interconnect Available | Interconnect Used | Half Interconnect Used |
+-------+------------------------+-------------------+------------------------+
| 0     | 128                    |  0 / 128 ( 0 % )  |  0 / 256 ( 0 % )       |
| 1     | 128                    |  0 / 128 ( 0 % )  |  0 / 256 ( 0 % )       |
| Total | 256                    |  0 / 256 ( 0 % )  |  0 / 512 ( 0 % )       |
+-------+------------------------+-------------------+------------------------+

+-----------------------------------------------------------------------------+
| Resource Usage Summary                                                      |
+-----------------------------------------------------------------------------+
+----------------------------+---------------------+
| Resource                   | Usage               |
+----------------------------+---------------------+
| Logic cells                | 5 / 1,200 ( < 1 % ) |
| Registers                  | 4 / 1,515 ( < 1 % ) |
| User inserted logic cells  | 0                   |
| I/O pins                   | 2 / 105 ( 1 % )     |
| Clock pins                 | 0                   |
| Dedicated input pins       | 0                   |
| Global signals             | 1                   |
| ESBs                       | 0 / 12 ( 0 % )      |
| Macrocells                 | 0 / 192 ( 0 % )     |
| ESB pterm bits used        | 0 / 24,576 ( 0 % )  |
| ESB CAM bits used          | 0 / 24,576 ( 0 % )  |
| Total memory bits          | 0 / 24,576 ( 0 % )  |
| Total RAM block bits       | 0 / 24,576 ( 0 % )  |
| FastRow interconnects      | 0 / 120 ( 0 % )     |
| PLLs                       | 0 / 2 ( 0 % )       |
| Maximum fan-out node       | fin_X_2             |
| Maximum fan-out            | 4                   |
| Total fan-out              | 12                  |
| Average fan-out            | 1.71                |
+----------------------------+---------------------+

+-----------------------------------------------------------------------------+
| Resource Utilization by Entity                                              |
+-----------------------------------------------------------------------------+
+----------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+
| Compilation Hierarchy Node             | Logic Cells | Registers | Memory Bits | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name                                         |
+----------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+
| |fr_div                                | 5 (2)       | 4         | 0           | 2    | 0            | 1 (1)        | 1 (1)             | 3 (0)            | |fr_div                                                     |
|    |lpm_counter:fv_rtl_0|              | 3 (0)       | 3         | 0           | 0    | 0            | 0 (0)        | 0 (0)             | 3 (0)            | |fr_div|lpm_counter:fv_rtl_0                                |
|       |alt_synch_counter:wysi_counter| | 3 (3)       | 3         | 0           | 0    | 0            | 0 (0)        | 0 (0)             | 3 (3)            | |fr_div|lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter |
+----------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+

+-----------------------------------------------------------------------------+
| Delay Chain Summary                                                         |
+-----------------------------------------------------------------------------+
+------+----------+-------------+-----------------------+-------------------------+---------------------+-----+
| Name | Pin Type | Pad to Core | Pad to Input Register | Core to Output Register | Core to CE Register | TCO |
+------+----------+-------------+-----------------------+-------------------------+---------------------+-----+
| Fin  | Input    | ON          | OFF                   | OFF                     | OFF                 | OFF |
| Fout | Output   | OFF         | OFF                   | OFF                     | OFF                 | OFF |
+------+----------+-------------+-----------------------+-------------------------+---------------------+-----+

+-----------------------------------------------------------------------------+
| I/O Bank Usage                                                              |
+-----------------------------------------------------------------------------+
+--------+----------------+
| Bank # | Usage          |
+--------+----------------+
| 1      | 0 / 15 ( 0 % ) |
| 2      | 0 / 13 ( 0 % ) |
| 3      | 1 / 11 ( 9 % ) |
| 4      | 1 / 12 ( 8 % ) |
| 5      | 0 / 14 ( 0 % ) |
| 6      | 0 / 12 ( 0 % ) |
| 7      | 0 / 6 ( 0 % )  |
| 8      | 0 / 9 ( 0 % )  |
+--------+----------------+

+-----------------------------------------------------------------------------+
| Equations                                                                   |
+-----------------------------------------------------------------------------+
The equations can be found in c:\qdesigns\fr_div\fr_div.eqn.htm.

+-----------------------------------------------------------------------------+
| Pin-Out File                                                                |
+-----------------------------------------------------------------------------+
The pin-out file can be found in c:\qdesigns\fr_div\fr_div.pin.

+-----------------------------------------------------------------------------+
| Timing Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------+------------------+------------------------------------------------------------------+--------------------+
| Assignment File | Source Name | Destination Name | Option                                                           | Setting            |
+-----------------+-------------+------------------+------------------------------------------------------------------+--------------------+
| fr_div.psf      |             |                  | Include external delays to/from device pins in fmax calculations | Off                |
| fr_div.psf      |             |                  | Run All Timing Analyses                                          | Off                |
| fr_div.psf      |             |                  | Ignore user-defined clock settings                               | Off                |
| fr_div.psf      |             |                  | Default hold multicycle                                          | Same As Multicycle |
| fr_div.psf      |             |                  | Cut off feedback from I/O pins                                   | On                 |
| fr_div.psf      |             |                  | Cut off clear and preset signal paths                            | On                 |
| fr_div.psf      |             |                  | Cut off read during write signal paths                           | On                 |
| fr_div.psf      |             |                  | Cut paths between unrelated clock domains                        | On                 |
| fr_div.psf      |             |                  | Number of paths to report                                        | 200                |
| fr_div.psf      |             |                  | Number of destination nodes to report                            | 10                 |
| fr_div.psf      |             |                  | Number of source nodes to report per destination node            | 10                 |
| fr_div.psf      |             |                  | Maximum Strongly Connected Component loop size                   | 50                 |
|                 |             |                  | Device name                                                      | EP20K30ETC144-1    |
+-----------------+-------------+------------------+------------------------------------------------------------------+--------------------+

+-----------------------------------------------------------------------------+
| fmax (not incl. delays to/from pins)                                        |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------------------+---------------+--------------------------+
| Clock Name                                                                 | Required fmax | Actual fmax (period)     |
|    -- Destination Register Name                                            |               |                          |
|       -- Source Register Name                                              |               |                          |
+----------------------------------------------------------------------------+---------------+--------------------------+
| Fin                                                                        | None          | Restricted to 279.02 MHz |
|    -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2]    | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | None          | Restricted to 279.02 MHz |
|    -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1]    | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | None          | Restricted to 279.02 MHz |
|    -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0]    | None          | Restricted to 279.02 MHz |
|       -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | None          | Restricted to 279.02 MHz |
|    -- rgF                                                                  | None          | Restricted to 279.02 MHz |
|       -- rgF                                                               | None          | Restricted to 279.02 MHz |
+----------------------------------------------------------------------------+---------------+--------------------------+

+-----------------------------------------------------------------------------+
| Register-to-Register fmax                                                   |
+-----------------------------------------------------------------------------+
+-------------------------------------------------------------------+-------------------------------------------------------------------+-------------------+------------------------+---------------+--------------------------+
| Source Register Name                                              | Destination Register Name                                         | Source Clock Name | Destination Clock Name | Required fmax | Actual fmax (period)     |
+-------------------------------------------------------------------+-------------------------------------------------------------------+-------------------+------------------------+---------------+--------------------------+
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[0] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| rgF                                                               | rgF                                                               | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
| lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | Fin               | Fin                    | None          | Restricted to 279.02 MHz |
+-------------------------------------------------------------------+-------------------------------------------------------------------+-------------------+------------------------+---------------+--------------------------+

+-----------------------------------------------------------------------------+
| tco (Clock to Output Delays)                                                |
+-----------------------------------------------------------------------------+
+-------------------------------------------------------------------------+------------+
| Output Name                                                             | Actual tco |
|    -- Register Name                                                     |            |
|       -- Clock Name                                                     |            |
+-------------------------------------------------------------------------+------------+
| Fout                                                                    | 12.695 ns  |
|    -- lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2] | 12.695 ns  |
|       -- Fin                                                            | 12.695 ns  |
+-------------------------------------------------------------------------+------------+

+-----------------------------------------------------------------------------+
| Processing Time                                                             |
+-----------------------------------------------------------------------------+
+-------------------+--------------+
| Module Name       | Elapsed Time |
+-------------------+--------------+
| Database Builder  | 00:00:01     |
| Logic Synthesizer | 00:00:00     |
| Fitter            | 00:00:01     |
| Assembler         | 00:00:00     |
| Timing Analyzer   | 00:00:00     |
| Total             | 00:00:04     |
+-------------------+--------------+