fr_div.csf.rpt

DDS divider clock AHDL

fr_div - Quartus II Compilation Report File
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+---------------------------------------------------------------+
| Report Information                                            |
+--------------------+------------------------------------------+
| Project            | c:\qdesigns\fr_div/                      |
| Compiler Settings  | fr_div                                   |
| Quartus II Version | 2.2 Build 147 12/02/2002 SJ Full Version |
+--------------------+------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "fr_div" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Logic Options
            Synthesis Section
                Resource Utilization by Entity
            Device Options
            Floorplan View
            Resource Section
                Input Pins
                Output Pins
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Carry Chains
                Non-Global High Fan-Out Signals
                Local Routing Interconnect
                MegaLAB Interconnect
                LAB External Interconnect
                MegaLAB Usage Summary
                Row Interconnect
                LAB Column Interconnect
                ESB Column Interconnect
                Resource Usage Summary
                Resource Utilization by Entity
                Delay Chain Summary
                I/O Bank Usage
            Equations
            Pin-Out File
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
| Legal Notice                                                                |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
| General Settings                                                            |
+-----------------------------------------------------------------------------+
+-------------------+---------------------+
| Option            | Setting             |
+-------------------+---------------------+
| Start date & time | 04/28/2009 21:08:37 |
| Main task         | Compilation         |
| Settings name     | fr_div              |
+-------------------+---------------------+

+-----------------------------------------------------------------------------+
| Summary                                                                     |
+-----------------------------------------------------------------------------+
+-------------------------------------+-----------------------------------------------+
| Processing status                   | Fitting Successful - Tue Apr 28 21:08:44 2009 |
| Timing requirements/analysis status | No requirements                               |
| Chip name                           | fr_div                                        |
| Device for compilation              | EP20K30ETC144-1                               |
| Total logic elements                | 5 / 1,200 ( < 1 % )                           |
| Total pins                          | 2 / 105 ( 1 % )                               |
| Total memory bits                   | 0 / 24,576 ( 0 % )                            |
| Total PLLs                          | 0 / 2 ( 0 % )                                 |
| Device for timing analysis          | EP20K30ETC144-1                               |
+-------------------------------------+-----------------------------------------------+

+-----------------------------------------------------------------------------+
| Compiler Settings                                                           |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------+--------------------+
| Option                                                   | Setting            |
+----------------------------------------------------------+--------------------+
| Chip name                                                | fr_div             |
| Family name                                              | APEX20KE           |
| Focus entity name                                        | |fr_div            |
| Device                                                   | AUTO               |
| Disk space/compilation speed tradeoff                    | Normal             |
| Preserve fewer node names                                | On                 |
| Optimize timing                                          | Normal Compilation |
| Optimize IOC register placement for timing               | On                 |
| Fast Fit compilation                                     | Off                |
| Perform WYSIWYG primitive resynthesis                    | Off                |
| Perform gate-level register retiming                     | Off                |
| Use Fitter timing information during synthesis           | Off                |
| Duplicate logic elements during fitting                  | Off                |
| Duplicate logic elements/resythesize LUTs during fitting | Off                |
| SignalProbe compilation                                  | Off                |
| Generate compressed bitstreams                           | Off                |
+----------------------------------------------------------+--------------------+

+-----------------------------------------------------------------------------+
| Messages                                                                    |
+-----------------------------------------------------------------------------+
Info: Found 1 design units and 1 entities in source file c:\qdesigns\fr_div\fr_div.tdf
  Info: Found entity 1: fr_div
Warning: Reduced register fv[0] with stuck data_in port to stuck value GND
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_counter.tdf
  Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\alt_synch_counter.tdf
  Info: Found entity 1: alt_synch_counter
Info: Implemented 7 device resources
  Info: Implemented 1 input pins
  Info: Implemented 1 output pins
  Info: Implemented 5 logic cells
Info: Automatically selected device EP20K30ETC144-1 for design fr_div
Info: Smart compilation turned off -- SignalProbe information will not be saved
Info: Promoted cell fin_X_2 to global signal automatically
Info: Started  fitting attempt 1 on Tue Apr 28 2009 at 21:08:43
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 2.198 ns
  Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1]'
  Info: 2: + IC(0.246 ns) + CELL(1.122 ns) = 1.529 ns; Loc. = LAB_1_A2; COMB Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT'
  Info: 3: + IC(0.000 ns) + CELL(0.669 ns) = 2.198 ns; Loc. = LAB_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2]'
  Info: Total cell delay = 1.952 ns
  Info: Total interconnect delay = 0.246 ns
Info: Found combinatorial loop of 2 nodes
  Info: Node fin_X_2
  Info: Node rgF
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node Fin is an undefined clock
Info: Clock Fin Internal fmax is restricted to 279.02 MHz between source register lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1] and destination register lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2]
  Info: fmax restricted to clock pin edge rate 3.584 ns. Expand message to see actual delay path.
    Info: + Longest register to register delay is 1.753 ns
      Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC2_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1]'
      Info: 2: + IC(0.253 ns) + CELL(0.670 ns) = 1.084 ns; Loc. = LC2_1_A2; COMB Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT'
      Info: 3: + IC(0.000 ns) + CELL(0.669 ns) = 1.753 ns; Loc. = LC3_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2]'
      Info: Total cell delay = 1.500 ns
      Info: Total interconnect delay = 0.253 ns
    Info: - Smallest clock skew is 0.000 ns
      Info: + Shortest clock path from clock Fin to destination register is 9.543 ns
        Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_25; CLK Node = 'Fin'
        Info: 2: + IC(0.000 ns) + CELL(4.714 ns) = 5.954 ns; Loc. = LC3_3_D1; COMB LOOP Node = 'fin_X_2'
          Info: Loc. = LC3_2_D1; Node rgF
        Info: 3: + IC(3.589 ns) + CELL(0.000 ns) = 9.543 ns; Loc. = LC3_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[2]'
        Info: Total cell delay = 5.954 ns
        Info: Total interconnect delay = 3.589 ns
      Info: - Longest clock path from clock Fin to source register is 9.543 ns
        Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_25; CLK Node = 'Fin'
        Info: 2: + IC(0.000 ns) + CELL(4.714 ns) = 5.954 ns; Loc. = LC3_3_D1; COMB LOOP Node = 'fin_X_2'
          Info: Loc. = LC3_2_D1; Node rgF
        Info: 3: + IC(3.589 ns) + CELL(0.000 ns) = 9.543 ns; Loc. = LC2_1_A2; REG Node = 'lpm_counter:fv_rtl_0|alt_synch_counter:wysi_counter|sload_path[1]'
        Info: Total cell delay = 5.954 ns
        Info: Total interconnect delay = 3.589 ns
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Micro setup delay of destination is 0.198 ns