_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 29 行

library verilog;
use verilog.vl_types.all;
entity IDC is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        q1              : in     vl_logic;
        q4              : in     vl_logic;
        instrIR_i       : in     vl_logic_vector(13 downto 0);
        Cda_ALU_o       : out    vl_logic_vector(3 downto 0);
        selalumux_o     : out    vl_logic;
        seladdrmux_o    : out    vl_logic;
        push_o          : out    vl_logic;
        pop_o           : out    vl_logic;
        write_ram_o     : out    vl_logic;
        read_ram_o      : out    vl_logic;
        writeW_o        : out    vl_logic;
        load_k_to_pc_o  : out    vl_logic;
        writeCARRY_o    : out    vl_logic;
        writeZ_o        : out    vl_logic;
        writeDC_o       : out    vl_logic;
        writePCLATH_o   : out    vl_logic;
        writePCL_o      : out    vl_logic;
        incrementpc_o   : out    vl_logic;
        skip_flag_i     : in     vl_logic;
        flag_zero_i     : in     vl_logic
    );
end IDC;