_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 30 行

library verilog;
use verilog.vl_types.all;
entity RAM is
    port(
        Z_i             : in     vl_logic;
        C_i             : in     vl_logic;
        DC_i            : in     vl_logic;
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        q4              : in     vl_logic;
        q2              : in     vl_logic;
        C_o             : out    vl_logic;
        write_ram_i     : in     vl_logic;
        read_ram_i      : in     vl_logic;
        memdata_i       : in     vl_logic_vector(7 downto 0);
        memdata_o       : out    vl_logic_vector(7 downto 0);
        addr_i          : in     vl_logic_vector(7 downto 0);
        PCLATH_o        : out    vl_logic_vector(4 downto 0);
        PCL_o           : out    vl_logic_vector(7 downto 0);
        writeCARRY_i    : in     vl_logic;
        writeZ_i        : in     vl_logic;
        writeDC_i       : in     vl_logic;
        writePCLATH_i   : in     vl_logic;
        newPC_i         : in     vl_logic_vector(12 downto 0);
        q1              : in     vl_logic;
        writePCL_i      : in     vl_logic;
        FSR_o           : out    vl_logic_vector(7 downto 0)
    );
end RAM;