_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity PC is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        pc_o            : out    vl_logic_vector(12 downto 0);
        q4              : in     vl_logic;
        Pc_Stack_i      : in     vl_logic_vector(12 downto 0);
        PCL_i           : in     vl_logic_vector(7 downto 0);
        PCLATH_i        : in     vl_logic_vector(4 downto 0);
        K_FROM_IR       : in     vl_logic_vector(10 downto 0);
        load_k_to_pc_i  : in     vl_logic;
        incrementpc_i   : in     vl_logic;
        pop_i           : in     vl_logic
    );
end PC;