_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity PIC is
    port(
        instr_i         : in     vl_logic_vector(13 downto 0);
        addr_rom_o      : out    vl_logic_vector(12 downto 0);
        reset_n         : in     vl_logic;
        clk_in          : in     vl_logic;
        clk_out         : out    vl_logic
    );
end PIC;