_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity ALU is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        cda_alu_i       : in     vl_logic_vector(3 downto 0);
        q3              : in     vl_logic;
        a_i             : in     vl_logic_vector(7 downto 0);
        y_o             : out    vl_logic_vector(7 downto 0);
        b_i             : in     vl_logic_vector(7 downto 0);
        b_nr_i          : in     vl_logic_vector(2 downto 0);
        C_i             : in     vl_logic;
        C_o             : out    vl_logic;
        Z_o             : out    vl_logic;
        DC_o            : out    vl_logic
    );
end ALU;