_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity IR is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        instr           : in     vl_logic_vector(13 downto 0);
        instrIR_o       : out    vl_logic_vector(13 downto 0);
        q1              : in     vl_logic;
        q4              : in     vl_logic
    );
end IR;