_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity STACK is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        q2              : in     vl_logic;
        q4              : in     vl_logic;
        push_i          : in     vl_logic;
        pop_i           : in     vl_logic;
        dataSTACK_i     : in     vl_logic_vector(12 downto 0);
        dataSTACK_o     : out    vl_logic_vector(12 downto 0)
    );
end STACK;