_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ADDRMUX is
    port(
        addr_sel_i      : in     vl_logic;
        addr_regFSR_i   : in     vl_logic_vector(7 downto 0);
        addrIR_i        : in     vl_logic_vector(6 downto 0);
        addrmux_o       : out    vl_logic_vector(7 downto 0)
    );
end ADDRMUX;