_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity tb is
    port(
        clk_in          : out    vl_logic;
        reset_n         : out    vl_logic
    );
end tb;