_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ALUMUX is
    port(
        data_sel_i      : in     vl_logic;
        alumux_dout     : out    vl_logic_vector(7 downto 0);
        opcodeIR_i      : in     vl_logic_vector(7 downto 0);
        memfile_i       : in     vl_logic_vector(7 downto 0)
    );
end ALUMUX;