_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity PC is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        q4              : in     vl_logic;
        PC_mem          : out    vl_logic_vector(12 downto 0)
    );
end PC;