_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity FsrReg is
    port(
        WRegInC         : in     vl_logic_vector(7 downto 0);
        IndirectAddr    : out    vl_logic_vector(6 downto 0)
    );
end FsrReg;