_primary.vhd

the verilog code used to design a PIC uC

library verilog;
use verilog.vl_types.all;
entity IR is
    port(
        clk_in          : in     vl_logic;
        reset_n         : in     vl_logic;
        MemDataOut      : in     vl_logic_vector(13 downto 0);
        IR_data         : out    vl_logic_vector(13 downto 0);
        WRegInC         : out    vl_logic_vector(7 downto 0);
        WRegInA         : out    vl_logic_vector(7 downto 0)
    );
end IR;