_primary.vhd

来自「the verilog code used to design a PIC uC」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity MemorieProgram is
    port(
        MemDataOut      : out    vl_logic_vector(13 downto 0);
        PC_mem          : in     vl_logic_vector(12 downto 0)
    );
end MemorieProgram;