_primary.vhd

the verilog code used to design a PIC uC

library verilog;
use verilog.vl_types.all;
entity TimingGenerator is
    port(
        clk_in          : in     vl_logic;
        clk_out         : out    vl_logic;
        reset_n         : in     vl_logic;
        q1              : out    vl_logic;
        q2              : out    vl_logic;
        q3              : out    vl_logic;
        q4              : out    vl_logic
    );
end TimingGenerator;