multiply_test.v

verilog multiply algorithm

module multiply_test();

parameter width=8;      //lungimea operanzilor
parameter width1=16;     //lungimea produsului, dublul operanzilor

wire [width-1:0]  a,b;
wire              ck,reset,ld,tercnt;
wire [width1-1:0] produs;

multiply #(width,width1)        DUT(.ck(ck),
                                    .reset(reset),
                                    .ld(ld),
                                    .a(a),
                                    .b(b),
                                    .produs(produs),
                                    .tercnt(tercnt)
                                    );

multiply_tb #width TB(.ck(ck),
                      .reset(reset),
                      .ld(ld),
                      .a(a),
                      .b(b)
                      );

endmodule