multiply_tb.v

来自「verilog multiply algorithm」· Verilog 代码 · 共 28 行

module multiply_tb(ck,reset,ld,a,b);

parameter width=4;      //lungimea operanzilor

output  [width-1:0]  a,b;
output               ck,reset,ld;

reg     [width-1:0]  a,b;
reg                  ck,reset,ld;

always #10 ck<=~ck;

initial
 begin ck<=0;
       reset<=0;
       ld<='bx;
       a<='bx;
       b<='bx;
 
       #20 reset<=1;
           ld<=1;
           a<='d10;
           b<='d7;
      
       #20 ld<=0;
 end

endmodule