fcout.tan.qmsg

基于Quartus II的8位十六进制频率计的项目设计

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin fcout\[23\] fcout\[23\]~reg0 10.227 ns register " "Info: tco from clock \"clkin\" to destination pin \"fcout\[23\]\" through register \"fcout\[23\]~reg0\" is 10.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.178 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_H1 96 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 96; CLK Node = 'clkin'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns fcout\[23\]~reg0 2 REG LC_X35_Y14_N6 1 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X35_Y14_N6; Fanout = 1; REG Node = 'fcout\[23\]~reg0'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clkin fcout[23]~reg0 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clkin fcout[23]~reg0 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clkin {} clkin~out0 {} fcout[23]~reg0 {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.825 ns + Longest register pin " "Info: + Longest register to pin delay is 6.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fcout\[23\]~reg0 1 REG LC_X35_Y14_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y14_N6; Fanout = 1; REG Node = 'fcout\[23\]~reg0'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { fcout[23]~reg0 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.701 ns) + CELL(2.124 ns) 6.825 ns fcout\[23\] 2 PIN PIN_J1 0 " "Info: 2: + IC(4.701 ns) + CELL(2.124 ns) = 6.825 ns; Loc. = PIN_J1; Fanout = 0; PIN Node = 'fcout\[23\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.825 ns" { fcout[23]~reg0 fcout[23] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 31.12 % ) " "Info: Total cell delay = 2.124 ns ( 31.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.701 ns ( 68.88 % ) " "Info: Total interconnect delay = 4.701 ns ( 68.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.825 ns" { fcout[23]~reg0 fcout[23] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.825 ns" { fcout[23]~reg0 {} fcout[23] {} } { 0.000ns 4.701ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clkin fcout[23]~reg0 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clkin {} clkin~out0 {} fcout[23]~reg0 {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.825 ns" { fcout[23]~reg0 fcout[23] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.825 ns" { fcout[23]~reg0 {} fcout[23] {} } { 0.000ns 4.701ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 18 13:02:14 2009 " "Info: Processing ended: Sat Apr 18 13:02:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}