fcout.tan.qmsg

基于Quartus II的8位十六进制频率计的项目设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sysclk " "Info: Assuming node \"sysclk\" is an undefined clock" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 5 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sysclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 6 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sysclk register cnt\[8\] register cnt\[12\] 176.49 MHz 5.666 ns Internal " "Info: Clock \"sysclk\" has Internal fmax of 176.49 MHz between source register \"cnt\[8\]\" and destination register \"cnt\[12\]\" (period= 5.666 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.405 ns + Longest register register " "Info: + Longest register to register delay is 5.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[8\] 1 REG LC_X37_Y6_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X37_Y6_N2; Fanout = 4; REG Node = 'cnt\[8\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[8] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.598 ns) + CELL(0.292 ns) 1.890 ns Equal0~341 2 COMB LC_X40_Y5_N3 1 " "Info: 2: + IC(1.598 ns) + CELL(0.292 ns) = 1.890 ns; Loc. = LC_X40_Y5_N3; Fanout = 1; COMB Node = 'Equal0~341'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.890 ns" { cnt[8] Equal0~341 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.114 ns) 3.202 ns Equal0~343 3 COMB LC_X40_Y4_N5 1 " "Info: 3: + IC(1.198 ns) + CELL(0.114 ns) = 3.202 ns; Loc. = LC_X40_Y4_N5; Fanout = 1; COMB Node = 'Equal0~343'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { Equal0~341 Equal0~343 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.498 ns Equal0~348 4 COMB LC_X40_Y4_N6 9 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.498 ns; Loc. = LC_X40_Y4_N6; Fanout = 9; COMB Node = 'Equal0~348'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal0~343 Equal0~348 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.598 ns) + CELL(0.309 ns) 5.405 ns cnt\[12\] 5 REG LC_X38_Y5_N4 4 " "Info: 5: + IC(1.598 ns) + CELL(0.309 ns) = 5.405 ns; Loc. = LC_X38_Y5_N4; Fanout = 4; REG Node = 'cnt\[12\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.907 ns" { Equal0~348 cnt[12] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.829 ns ( 15.34 % ) " "Info: Total cell delay = 0.829 ns ( 15.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.576 ns ( 84.66 % ) " "Info: Total interconnect delay = 4.576 ns ( 84.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.405 ns" { cnt[8] Equal0~341 Equal0~343 Equal0~348 cnt[12] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.405 ns" { cnt[8] {} Equal0~341 {} Equal0~343 {} Equal0~348 {} cnt[12] {} } { 0.000ns 1.598ns 1.198ns 0.182ns 1.598ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"sysclk\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sysclk 1 CLK PIN_G1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 32; CLK Node = 'sysclk'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns cnt\[12\] 2 REG LC_X38_Y5_N4 4 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X38_Y5_N4; Fanout = 4; REG Node = 'cnt\[12\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { sysclk cnt[12] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[12] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[12] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk source 3.111 ns - Longest register " "Info: - Longest clock path from clock \"sysclk\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sysclk 1 CLK PIN_G1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 32; CLK Node = 'sysclk'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sysclk } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns cnt\[8\] 2 REG LC_X37_Y6_N2 4 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X37_Y6_N2; Fanout = 4; REG Node = 'cnt\[8\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { sysclk cnt[8] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[8] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[8] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[12] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[12] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[8] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[8] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.405 ns" { cnt[8] Equal0~341 Equal0~343 Equal0~348 cnt[12] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.405 ns" { cnt[8] {} Equal0~341 {} Equal0~343 {} Equal0~348 {} cnt[12] {} } { 0.000ns 1.598ns 1.198ns 0.182ns 1.598ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.309ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[12] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[12] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { sysclk cnt[8] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { sysclk {} sysclk~out0 {} cnt[8] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register cntp6\[0\] register cntp7\[2\] 153.09 MHz 6.532 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 153.09 MHz between source register \"cntp6\[0\]\" and destination register \"cntp7\[2\]\" (period= 6.532 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.280 ns + Longest register register " "Info: + Longest register to register delay is 6.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntp6\[0\] 1 REG LC_X32_Y15_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y15_N0; Fanout = 6; REG Node = 'cntp6\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cntp6[0] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.292 ns) 1.532 ns Equal6~34 2 COMB LC_X32_Y15_N3 4 " "Info: 2: + IC(1.240 ns) + CELL(0.292 ns) = 1.532 ns; Loc. = LC_X32_Y15_N3; Fanout = 4; COMB Node = 'Equal6~34'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { cntp6[0] Equal6~34 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.590 ns) 3.407 ns cntp8~502 3 COMB LC_X32_Y16_N8 6 " "Info: 3: + IC(1.285 ns) + CELL(0.590 ns) = 3.407 ns; Loc. = LC_X32_Y16_N8; Fanout = 6; COMB Node = 'cntp8~502'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.875 ns" { Equal6~34 cntp8~502 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.114 ns) 4.349 ns cntp7~483 4 COMB LC_X31_Y16_N9 2 " "Info: 4: + IC(0.828 ns) + CELL(0.114 ns) = 4.349 ns; Loc. = LC_X31_Y16_N9; Fanout = 2; COMB Node = 'cntp7~483'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.942 ns" { cntp8~502 cntp7~483 } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(0.309 ns) 6.280 ns cntp7\[2\] 5 REG LC_X36_Y17_N4 5 " "Info: 5: + IC(1.622 ns) + CELL(0.309 ns) = 6.280 ns; Loc. = LC_X36_Y17_N4; Fanout = 5; REG Node = 'cntp7\[2\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.931 ns" { cntp7~483 cntp7[2] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.305 ns ( 20.78 % ) " "Info: Total cell delay = 1.305 ns ( 20.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.975 ns ( 79.22 % ) " "Info: Total interconnect delay = 4.975 ns ( 79.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { cntp6[0] Equal6~34 cntp8~502 cntp7~483 cntp7[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { cntp6[0] {} Equal6~34 {} cntp8~502 {} cntp7~483 {} cntp7[2] {} } { 0.000ns 1.240ns 1.285ns 0.828ns 1.622ns } { 0.000ns 0.292ns 0.590ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.009 ns - Smallest " "Info: - Smallest clock skew is 0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.187 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_H1 96 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 96; CLK Node = 'clkin'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.711 ns) 3.187 ns cntp7\[2\] 2 REG LC_X36_Y17_N4 5 " "Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X36_Y17_N4; Fanout = 5; REG Node = 'cntp7\[2\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.718 ns" { clkin cntp7[2] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.40 % ) " "Info: Total cell delay = 2.180 ns ( 68.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.60 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clkin cntp7[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clkin {} clkin~out0 {} cntp7[2] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.178 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_H1 96 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 96; CLK Node = 'clkin'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns cntp6\[0\] 2 REG LC_X32_Y15_N0 6 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X32_Y15_N0; Fanout = 6; REG Node = 'cntp6\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clkin cntp6[0] } "NODE_NAME" } } { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clkin cntp6[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clkin {} clkin~out0 {} cntp6[0] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clkin cntp7[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clkin {} clkin~out0 {} cntp7[2] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clkin cntp6[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clkin {} clkin~out0 {} cntp6[0] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fcout.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.280 ns" { cntp6[0] Equal6~34 cntp8~502 cntp7~483 cntp7[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.280 ns" { cntp6[0] {} Equal6~34 {} cntp8~502 {} cntp7~483 {} cntp7[2] {} } { 0.000ns 1.240ns 1.285ns 0.828ns 1.622ns } { 0.000ns 0.292ns 0.590ns 0.114ns 0.309ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { clkin cntp7[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { clkin {} clkin~out0 {} cntp7[2] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clkin cntp6[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clkin {} clkin~out0 {} cntp6[0] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}