fcout.vhd

基于Quartus II的8位十六进制频率计的项目设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fcout is
   port(sysclk: in std_logic;  -----20MHz sysyem clk
         clkin: in std_logic;
         fcout: out std_logic_vector(31 downto 0));
end;
architecture one of fcout is
   signal clk_cnt:std_logic;    
   signal     cnt:integer range 2147483647 downto 0;
   signal cntp1,cntp2,cntp3,cntp4,cntp5,cntp6,cntp7,cntp8:std_logic_vector(3 downto 0);
   signal cntq1,cntq2,cntq3,cntq4,cntq5,cntq6,cntq7,cntq8:std_logic_vector(3 downto 0);
begin
---------------------------0.5Hz frequancy_div-------------------
process(sysclk)
  begin
  if sysclk'event and sysclk='1' then
    if cnt=39999999 then clk_cnt<=not clk_cnt;cnt<=0;
    else cnt<=cnt+1;
    end if;
  end if;
end process;
---------------------------count in 1 second---------------------
process(clkin)
begin
 if clkin'event and clkin='1' then 
   if clk_cnt='1' then
     if cntp1="1001" then cntp1<="0000";
       if cntp2="1001" then cntp2<="0000";
         if cntp3="1001" then cntp3<="0000";
           if cntp4="1001" then cntp4<="0000";
             if cntp5="1001" then cntp5<="0000";
               if cntp6="1001" then cntp6<="0000";
                 if cntp7="1001" then cntp7<="0000";
                   if cntp8="1001" then cntp8<="0000";
                   else cntp8<=cntp8+1;end if;
                 else cntp7<=cntp7+1;end if; 
               else cntp6<=cntp6+1;end if; 
             else cntp5<=cntp5+1;end if;
           else cntp4<=cntp4+1;end if;
         else cntp3<=cntp3+1;end if;
       else cntp2<=cntp2+1;end if;
     else cntp1<=cntp1+1;end if;
   else 
      if cntp1/="0000" or cntp2/="0000" or cntp3/="0000" or
         cntp4/="0000" or cntp5/="0000" or cntp6/="0000" or
         cntp7/="0000" or cntp8/="0000" then
       cntq1<=cntp1;   cntq2<=cntp2;   cntq3<=cntp3;   
       cntq4<=cntp4;   cntq5<=cntp5;   cntq6<=cntp6;   
       cntq7<=cntp7;   cntq8<=cntp8;
       cntp1<="0000";  cntp2<="0000";  cntp3<="0000";   
       cntp4<="0000";  cntp5<="0000";  cntp6<="0000";   
       cntp7<="0000";  cntp8<="0000";
      fcout<=cntq8&cntq7&cntq6&cntq5&cntq4&cntq3&cntq2&cntq1;
      end if;
   end if;   
 end if; 
end process;   


end;