dvf.tan.rpt

来自「基于Quartus II的数控分频器的项目设计」· RPT 代码 · 共 288 行 · 第 1/3 页

+-------+--------------+------------+-------------+------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; -3.917 ns ; D[5] ; \P_CONT:CNT8[5] ; CLK      ;
; N/A           ; None        ; -4.301 ns ; D[2] ; \P_CONT:CNT8[2] ; CLK      ;
; N/A           ; None        ; -4.308 ns ; D[3] ; \P_CONT:CNT8[3] ; CLK      ;
; N/A           ; None        ; -4.544 ns ; D[6] ; \P_CONT:CNT8[6] ; CLK      ;
; N/A           ; None        ; -4.558 ns ; D[4] ; \P_CONT:CNT8[4] ; CLK      ;
; N/A           ; None        ; -4.583 ns ; D[0] ; \P_CONT:CNT8[0] ; CLK      ;
; N/A           ; None        ; -4.594 ns ; D[1] ; \P_CONT:CNT8[1] ; CLK      ;
; N/A           ; None        ; -4.720 ns ; D[7] ; \P_CONT:CNT8[7] ; CLK      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Apr 23 00:05:03 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DVF -c DVF --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "FULL" as buffer
Info: Clock "CLK" has Internal fmax of 259.47 MHz between source register "\P_CONT:CNT8[7]" and destination register "\P_CONT:CNT8[2]" (period= 3.854 ns)
    Info: + Longest register to register delay is 3.593 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\P_CONT:CNT8[7]'
        Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X11_Y16_N9; Fanout = 2; COMB Node = 'Equal0~65'
        Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.896 ns; Loc. = LC_X11_Y16_N8; Fanout = 8; COMB Node = 'Equal0~66'
        Info: 4: + IC(0.472 ns) + CELL(1.225 ns) = 3.593 ns; Loc. = LC_X11_Y16_N2; Fanout = 5; REG Node = '\P_CONT:CNT8[2]'
        Info: Total cell delay = 2.107 ns ( 58.64 % )
        Info: Total interconnect delay = 1.486 ns ( 41.36 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.246 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N2; Fanout = 5; REG Node = '\P_CONT:CNT8[2]'
            Info: Total cell delay = 2.180 ns ( 67.16 % )
            Info: Total interconnect delay = 1.066 ns ( 32.84 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.246 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\P_CONT:CNT8[7]'
            Info: Total cell delay = 2.180 ns ( 67.16 % )
            Info: Total interconnect delay = 1.066 ns ( 32.84 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "\P_CONT:CNT8[7]" (data pin = "D[7]", clock pin = "CLK") is 4.772 ns
    Info: + Longest pin to register delay is 7.981 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_M7; Fanout = 1; PIN Node = 'D[7]'
        Info: 2: + IC(6.391 ns) + CELL(0.115 ns) = 7.981 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\P_CONT:CNT8[7]'
        Info: Total cell delay = 1.590 ns ( 19.92 % )
        Info: Total interconnect delay = 6.391 ns ( 80.08 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\P_CONT:CNT8[7]'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: tco from clock "CLK" to destination pin "FOUT" through register "\P_DIV:CNT2" is 9.909 ns
    Info: + Longest clock path from clock "CLK" to source register is 4.957 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.066 ns) + CELL(0.935 ns) = 3.470 ns; Loc. = LC_X11_Y16_N8; Fanout = 1; REG Node = 'FULL'
        Info: 3: + IC(0.776 ns) + CELL(0.711 ns) = 4.957 ns; Loc. = LC_X10_Y16_N2; Fanout = 2; REG Node = '\P_DIV:CNT2'
        Info: Total cell delay = 3.115 ns ( 62.84 % )
        Info: Total interconnect delay = 1.842 ns ( 37.16 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y16_N2; Fanout = 2; REG Node = '\P_DIV:CNT2'
        Info: 2: + IC(2.620 ns) + CELL(2.108 ns) = 4.728 ns; Loc. = PIN_E6; Fanout = 0; PIN Node = 'FOUT'
        Info: Total cell delay = 2.108 ns ( 44.59 % )
        Info: Total interconnect delay = 2.620 ns ( 55.41 % )
Info: th for register "\P_CONT:CNT8[5]" (data pin = "D[5]", clock pin = "CLK") is -3.917 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N5; Fanout = 4; REG Node = '\P_CONT:CNT8[5]'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.178 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H5; Fanout = 1; PIN Node = 'D[5]'
        Info: 2: + IC(5.594 ns) + CELL(0.115 ns) = 7.178 ns; Loc. = LC_X11_Y16_N5; Fanout = 4; REG Node = '\P_CONT:CNT8[5]'
        Info: Total cell delay = 1.584 ns ( 22.07 % )
        Info: Total interconnect delay = 5.594 ns ( 77.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Thu Apr 23 00:05:04 2009
    Info: Elapsed time: 00:00:01