dvf.tan.qmsg

基于Quartus II的数控分频器的项目设计

{ "Info" "ITDB_TSU_RESULT" "\\P_CONT:CNT8\[7\] D\[7\] CLK 4.772 ns register " "Info: tsu for register \"\\P_CONT:CNT8\[7\]\" (data pin = \"D\[7\]\", clock pin = \"CLK\") is 4.772 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.981 ns + Longest pin register " "Info: + Longest pin to register delay is 7.981 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D\[7\] 1 PIN PIN_M7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_M7; Fanout = 1; PIN Node = 'D\[7\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.391 ns) + CELL(0.115 ns) 7.981 ns \\P_CONT:CNT8\[7\] 2 REG LC_X11_Y16_N7 2 " "Info: 2: + IC(6.391 ns) + CELL(0.115 ns) = 7.981 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\\P_CONT:CNT8\[7\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.506 ns" { D[7] \P_CONT:CNT8[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 19.92 % ) " "Info: Total cell delay = 1.590 ns ( 19.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.391 ns ( 80.08 % ) " "Info: Total interconnect delay = 6.391 ns ( 80.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "7.981 ns" { D[7] \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "7.981 ns" { D[7] {} D[7]~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 6.391ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.246 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns \\P_CONT:CNT8\[7\] 2 REG LC_X11_Y16_N7 2 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\\P_CONT:CNT8\[7\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "7.981 ns" { D[7] \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "7.981 ns" { D[7] {} D[7]~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 6.391ns } { 0.000ns 1.475ns 0.115ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT \\P_DIV:CNT2 9.909 ns register " "Info: tco from clock \"CLK\" to destination pin \"FOUT\" through register \"\\P_DIV:CNT2\" is 9.909 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 4.957 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 4.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.935 ns) 3.470 ns FULL 2 REG LC_X11_Y16_N8 1 " "Info: 2: + IC(1.066 ns) + CELL(0.935 ns) = 3.470 ns; Loc. = LC_X11_Y16_N8; Fanout = 1; REG Node = 'FULL'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.001 ns" { CLK FULL } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.711 ns) 4.957 ns \\P_DIV:CNT2 3 REG LC_X10_Y16_N2 2 " "Info: 3: + IC(0.776 ns) + CELL(0.711 ns) = 4.957 ns; Loc. = LC_X10_Y16_N2; Fanout = 2; REG Node = '\\P_DIV:CNT2'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.487 ns" { FULL \P_DIV:CNT2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 62.84 % ) " "Info: Total cell delay = 3.115 ns ( 62.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.842 ns ( 37.16 % ) " "Info: Total interconnect delay = 1.842 ns ( 37.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.957 ns" { CLK FULL \P_DIV:CNT2 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.957 ns" { CLK {} CLK~out0 {} FULL {} \P_DIV:CNT2 {} } { 0.000ns 0.000ns 1.066ns 0.776ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.728 ns + Longest register pin " "Info: + Longest register to pin delay is 4.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\P_DIV:CNT2 1 REG LC_X10_Y16_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y16_N2; Fanout = 2; REG Node = '\\P_DIV:CNT2'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { \P_DIV:CNT2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.620 ns) + CELL(2.108 ns) 4.728 ns FOUT 2 PIN PIN_E6 0 " "Info: 2: + IC(2.620 ns) + CELL(2.108 ns) = 4.728 ns; Loc. = PIN_E6; Fanout = 0; PIN Node = 'FOUT'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.728 ns" { \P_DIV:CNT2 FOUT } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 44.59 % ) " "Info: Total cell delay = 2.108 ns ( 44.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.620 ns ( 55.41 % ) " "Info: Total interconnect delay = 2.620 ns ( 55.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.728 ns" { \P_DIV:CNT2 FOUT } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.728 ns" { \P_DIV:CNT2 {} FOUT {} } { 0.000ns 2.620ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.957 ns" { CLK FULL \P_DIV:CNT2 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.957 ns" { CLK {} CLK~out0 {} FULL {} \P_DIV:CNT2 {} } { 0.000ns 0.000ns 1.066ns 0.776ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.728 ns" { \P_DIV:CNT2 FOUT } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.728 ns" { \P_DIV:CNT2 {} FOUT {} } { 0.000ns 2.620ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "\\P_CONT:CNT8\[5\] D\[5\] CLK -3.917 ns register " "Info: th for register \"\\P_CONT:CNT8\[5\]\" (data pin = \"D\[5\]\", clock pin = \"CLK\") is -3.917 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.246 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns \\P_CONT:CNT8\[5\] 2 REG LC_X11_Y16_N5 4 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N5; Fanout = 4; REG Node = '\\P_CONT:CNT8\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { CLK \P_CONT:CNT8[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[5] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.178 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D\[5\] 1 PIN PIN_H5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H5; Fanout = 1; PIN Node = 'D\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.594 ns) + CELL(0.115 ns) 7.178 ns \\P_CONT:CNT8\[5\] 2 REG LC_X11_Y16_N5 4 " "Info: 2: + IC(5.594 ns) + CELL(0.115 ns) = 7.178 ns; Loc. = LC_X11_Y16_N5; Fanout = 4; REG Node = '\\P_CONT:CNT8\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.709 ns" { D[5] \P_CONT:CNT8[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 22.07 % ) " "Info: Total cell delay = 1.584 ns ( 22.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.594 ns ( 77.93 % ) " "Info: Total interconnect delay = 5.594 ns ( 77.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "7.178 ns" { D[5] \P_CONT:CNT8[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "7.178 ns" { D[5] {} D[5]~out0 {} \P_CONT:CNT8[5] {} } { 0.000ns 0.000ns 5.594ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[5] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "7.178 ns" { D[5] \P_CONT:CNT8[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "7.178 ns" { D[5] {} D[5]~out0 {} \P_CONT:CNT8[5] {} } { 0.000ns 0.000ns 5.594ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 00:05:04 2009 " "Info: Processing ended: Thu Apr 23 00:05:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}