dvf.tan.qmsg

基于Quartus II的数控分频器的项目设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 00:05:03 2009 " "Info: Processing started: Thu Apr 23 00:05:03 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DVF -c DVF --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DVF -c DVF --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FULL " "Info: Detected ripple clock \"FULL\" as buffer" {  } { { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 10 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FULL" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register \\P_CONT:CNT8\[7\] register \\P_CONT:CNT8\[2\] 259.47 MHz 3.854 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 259.47 MHz between source register \"\\P_CONT:CNT8\[7\]\" and destination register \"\\P_CONT:CNT8\[2\]\" (period= 3.854 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.593 ns + Longest register register " "Info: + Longest register to register delay is 3.593 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\P_CONT:CNT8\[7\] 1 REG LC_X11_Y16_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\\P_CONT:CNT8\[7\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { \P_CONT:CNT8[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.590 ns) 1.142 ns Equal0~65 2 COMB LC_X11_Y16_N9 2 " "Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X11_Y16_N9; Fanout = 2; COMB Node = 'Equal0~65'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { \P_CONT:CNT8[7] Equal0~65 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.292 ns) 1.896 ns Equal0~66 3 COMB LC_X11_Y16_N8 8 " "Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.896 ns; Loc. = LC_X11_Y16_N8; Fanout = 8; COMB Node = 'Equal0~66'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { Equal0~65 Equal0~66 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(1.225 ns) 3.593 ns \\P_CONT:CNT8\[2\] 4 REG LC_X11_Y16_N2 5 " "Info: 4: + IC(0.472 ns) + CELL(1.225 ns) = 3.593 ns; Loc. = LC_X11_Y16_N2; Fanout = 5; REG Node = '\\P_CONT:CNT8\[2\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { Equal0~66 \P_CONT:CNT8[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.107 ns ( 58.64 % ) " "Info: Total cell delay = 2.107 ns ( 58.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.486 ns ( 41.36 % ) " "Info: Total interconnect delay = 1.486 ns ( 41.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.593 ns" { \P_CONT:CNT8[7] Equal0~65 Equal0~66 \P_CONT:CNT8[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.593 ns" { \P_CONT:CNT8[7] {} Equal0~65 {} Equal0~66 {} \P_CONT:CNT8[2] {} } { 0.000ns 0.552ns 0.462ns 0.472ns } { 0.000ns 0.590ns 0.292ns 1.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.246 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns \\P_CONT:CNT8\[2\] 2 REG LC_X11_Y16_N2 5 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N2; Fanout = 5; REG Node = '\\P_CONT:CNT8\[2\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { CLK \P_CONT:CNT8[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[2] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.246 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_H1 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 9; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DVF.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/fdiv/DVF.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns \\P_CONT:CNT8\[7\] 2 REG LC_X11_Y16_N7 2 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N7; Fanout = 2; REG Node = '\\P_CONT:CNT8\[7\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[2] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.593 ns" { \P_CONT:CNT8[7] Equal0~65 Equal0~66 \P_CONT:CNT8[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.593 ns" { \P_CONT:CNT8[7] {} Equal0~65 {} Equal0~66 {} \P_CONT:CNT8[2] {} } { 0.000ns 0.552ns 0.462ns 0.472ns } { 0.000ns 0.590ns 0.292ns 1.225ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[2] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[2] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { CLK \P_CONT:CNT8[7] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { CLK {} CLK~out0 {} \P_CONT:CNT8[7] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}