count10.vhd

来自「基于Quartus II的十进制加法计数器的项目设计」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT10 IS
   PORT(CLK,RST,EN:IN STD_LOGIC;
                CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
               COUT:OUT STD_LOGIC);
END COUNT10;
ARCHITECTURE behav OF COUNT10 IS
BEGIN
   PROCESS(CLK,RST,EN)
     VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
   BEGIN
      IF RST='1'THEN CQI:=(OTHERS=>'0');
      ELSIF CLK'EVENT AND CLK='1'THEN 
       IF EN='1'THEN
        IF CQI<9 THEN CQI:=CQI+1;
          ELSE CQI:=(OTHERS=>'0');END IF;
       END IF;
      END IF;
    IF CQI=9 THEN COUT<='1';
      ELSE COUT<='0';END IF;
     CQ<=CQI;
   END PROCESS;
END behav;