epd.vhd

来自「完整的等精度频率相位计」· VHDL 代码 · 共 97 行

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY epd IS 
	port
	(
		PA :  IN  STD_LOGIC;
		PB :  IN  STD_LOGIC;
		EPD :  OUT  STD_LOGIC
	);
END epd;

ARCHITECTURE bdf_type OF epd IS 

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_17 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_13 :  STD_LOGIC;


BEGIN 
EPD <= SYNTHESIZED_WIRE_14;
SYNTHESIZED_WIRE_16 <= '0';
SYNTHESIZED_WIRE_19 <= '0';



SYNTHESIZED_WIRE_0 <= NOT(PA);


SYNTHESIZED_WIRE_2 <= NOT(PB);


SYNTHESIZED_WIRE_17 <= NOT(SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1);

SYNTHESIZED_WIRE_15 <= NOT(SYNTHESIZED_WIRE_14 AND SYNTHESIZED_WIRE_2);

process(SYNTHESIZED_WIRE_16,SYNTHESIZED_WIRE_15,SYNTHESIZED_WIRE_17)
begin
if (SYNTHESIZED_WIRE_15 = '0') then
	SYNTHESIZED_WIRE_18 <= '0';
elsif (SYNTHESIZED_WIRE_17 = '0') then
	SYNTHESIZED_WIRE_18 <= '1';
elsif (rising_edge(SYNTHESIZED_WIRE_16)) then
	SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_16;
end if;
end process;

SYNTHESIZED_WIRE_13 <= NOT(SYNTHESIZED_WIRE_18 AND SYNTHESIZED_WIRE_17);

SYNTHESIZED_WIRE_10 <= NOT(SYNTHESIZED_WIRE_15 AND SYNTHESIZED_WIRE_9);

SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_18);


process(SYNTHESIZED_WIRE_19,SYNTHESIZED_WIRE_10,SYNTHESIZED_WIRE_13)
begin
if (SYNTHESIZED_WIRE_10 = '0') then
	SYNTHESIZED_WIRE_14 <= '0';
elsif (SYNTHESIZED_WIRE_13 = '0') then
	SYNTHESIZED_WIRE_14 <= '1';
elsif (rising_edge(SYNTHESIZED_WIRE_19)) then
	SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19;
end if;
end process;

SYNTHESIZED_WIRE_1 <= NOT(SYNTHESIZED_WIRE_14);


END;