prev_cmp_efcount.tan.qmsg

完整的等精度频率相位计

{ "Info" "ITDB_FULL_TCO_RESULT" "CL EEND efcount:b2v_inst1\|q2 17.069 ns register " "Info: tco from clock \"CL\" to destination pin \"EEND\" through register \"efcount:b2v_inst1\|q2\" is 17.069 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CL source 10.233 ns + Longest register " "Info: + Longest clock path from clock \"CL\" to source register is 10.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CL 1 CLK PIN_J1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 2; CLK Node = 'CL'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CL } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.982 ns) + CELL(0.292 ns) 3.743 ns efcount:b2v_inst1\|ma 2 COMB LC_X8_Y13_N5 2 " "Info: 2: + IC(1.982 ns) + CELL(0.292 ns) = 3.743 ns; Loc. = LC_X8_Y13_N5; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|ma'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { CL efcount:b2v_inst1|ma } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.935 ns) 5.163 ns efcount:b2v_inst1\|q1 3 REG LC_X8_Y13_N2 1 " "Info: 3: + IC(0.485 ns) + CELL(0.935 ns) = 5.163 ns; Loc. = LC_X8_Y13_N2; Fanout = 1; REG Node = 'efcount:b2v_inst1\|q1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.420 ns" { efcount:b2v_inst1|ma efcount:b2v_inst1|q1 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.292 ns) 5.998 ns efcount:b2v_inst1\|clk2 4 COMB LC_X8_Y13_N0 2 " "Info: 4: + IC(0.543 ns) + CELL(0.292 ns) = 5.998 ns; Loc. = LC_X8_Y13_N0; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|clk2'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.835 ns" { efcount:b2v_inst1|q1 efcount:b2v_inst1|clk2 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.524 ns) + CELL(0.711 ns) 10.233 ns efcount:b2v_inst1\|q2 5 REG LC_X8_Y12_N2 2 " "Info: 5: + IC(3.524 ns) + CELL(0.711 ns) = 10.233 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'efcount:b2v_inst1\|q2'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.235 ns" { efcount:b2v_inst1|clk2 efcount:b2v_inst1|q2 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.699 ns ( 36.15 % ) " "Info: Total cell delay = 3.699 ns ( 36.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.534 ns ( 63.85 % ) " "Info: Total interconnect delay = 6.534 ns ( 63.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "10.233 ns" { CL efcount:b2v_inst1|ma efcount:b2v_inst1|q1 efcount:b2v_inst1|clk2 efcount:b2v_inst1|q2 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "10.233 ns" { CL {} CL~out0 {} efcount:b2v_inst1|ma {} efcount:b2v_inst1|q1 {} efcount:b2v_inst1|clk2 {} efcount:b2v_inst1|q2 {} } { 0.000ns 0.000ns 1.982ns 0.485ns 0.543ns 3.524ns } { 0.000ns 1.469ns 0.292ns 0.935ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.612 ns + Longest register pin " "Info: + Longest register to pin delay is 6.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns efcount:b2v_inst1\|q2 1 REG LC_X8_Y12_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'efcount:b2v_inst1\|q2'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { efcount:b2v_inst1|q2 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.309 ns) + CELL(0.590 ns) 1.899 ns efcount:b2v_inst1\|Equal8~13 2 COMB LC_X8_Y13_N7 1 " "Info: 2: + IC(1.309 ns) + CELL(0.590 ns) = 1.899 ns; Loc. = LC_X8_Y13_N7; Fanout = 1; COMB Node = 'efcount:b2v_inst1\|Equal8~13'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.899 ns" { efcount:b2v_inst1|q2 efcount:b2v_inst1|Equal8~13 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.589 ns) + CELL(2.124 ns) 6.612 ns EEND 3 PIN PIN_L3 0 " "Info: 3: + IC(2.589 ns) + CELL(2.124 ns) = 6.612 ns; Loc. = PIN_L3; Fanout = 0; PIN Node = 'EEND'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.713 ns" { efcount:b2v_inst1|Equal8~13 EEND } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns ( 41.05 % ) " "Info: Total cell delay = 2.714 ns ( 41.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.898 ns ( 58.95 % ) " "Info: Total interconnect delay = 3.898 ns ( 58.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.612 ns" { efcount:b2v_inst1|q2 efcount:b2v_inst1|Equal8~13 EEND } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.612 ns" { efcount:b2v_inst1|q2 {} efcount:b2v_inst1|Equal8~13 {} EEND {} } { 0.000ns 1.309ns 2.589ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "10.233 ns" { CL efcount:b2v_inst1|ma efcount:b2v_inst1|q1 efcount:b2v_inst1|clk2 efcount:b2v_inst1|q2 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "10.233 ns" { CL {} CL~out0 {} efcount:b2v_inst1|ma {} efcount:b2v_inst1|q1 {} efcount:b2v_inst1|clk2 {} efcount:b2v_inst1|q2 {} } { 0.000ns 0.000ns 1.982ns 0.485ns 0.543ns 3.524ns } { 0.000ns 1.469ns 0.292ns 0.935ns 0.292ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.612 ns" { efcount:b2v_inst1|q2 efcount:b2v_inst1|Equal8~13 EEND } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.612 ns" { efcount:b2v_inst1|q2 {} efcount:b2v_inst1|Equal8~13 {} EEND {} } { 0.000ns 1.309ns 2.589ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SEL\[0\] DATA\[5\] 17.513 ns Longest " "Info: Longest tpd from source pin \"SEL\[0\]\" to destination pin \"DATA\[5\]\" is 17.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SEL\[0\] 1 PIN PIN_H5 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H5; Fanout = 24; PIN Node = 'SEL\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEL[0] } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.054 ns) + CELL(0.292 ns) 8.815 ns efcount:b2v_inst1\|data\[5\]~339 2 COMB LC_X9_Y15_N9 1 " "Info: 2: + IC(7.054 ns) + CELL(0.292 ns) = 8.815 ns; Loc. = LC_X9_Y15_N9; Fanout = 1; COMB Node = 'efcount:b2v_inst1\|data\[5\]~339'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "7.346 ns" { SEL[0] efcount:b2v_inst1|data[5]~339 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 10.647 ns efcount:b2v_inst1\|data\[5\]~340 3 COMB LC_X10_Y13_N7 1 " "Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 10.647 ns; Loc. = LC_X10_Y13_N7; Fanout = 1; COMB Node = 'efcount:b2v_inst1\|data\[5\]~340'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.832 ns" { efcount:b2v_inst1|data[5]~339 efcount:b2v_inst1|data[5]~340 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.521 ns) + CELL(0.590 ns) 12.758 ns efcount:b2v_inst1\|data\[5\]~341 4 COMB LC_X8_Y14_N9 1 " "Info: 4: + IC(1.521 ns) + CELL(0.590 ns) = 12.758 ns; Loc. = LC_X8_Y14_N9; Fanout = 1; COMB Node = 'efcount:b2v_inst1\|data\[5\]~341'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.111 ns" { efcount:b2v_inst1|data[5]~340 efcount:b2v_inst1|data[5]~341 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.647 ns) + CELL(2.108 ns) 17.513 ns DATA\[5\] 5 PIN PIN_M6 0 " "Info: 5: + IC(2.647 ns) + CELL(2.108 ns) = 17.513 ns; Loc. = PIN_M6; Fanout = 0; PIN Node = 'DATA\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.755 ns" { efcount:b2v_inst1|data[5]~341 DATA[5] } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.049 ns ( 28.83 % ) " "Info: Total cell delay = 5.049 ns ( 28.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.464 ns ( 71.17 % ) " "Info: Total interconnect delay = 12.464 ns ( 71.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "17.513 ns" { SEL[0] efcount:b2v_inst1|data[5]~339 efcount:b2v_inst1|data[5]~340 efcount:b2v_inst1|data[5]~341 DATA[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "17.513 ns" { SEL[0] {} SEL[0]~out0 {} efcount:b2v_inst1|data[5]~339 {} efcount:b2v_inst1|data[5]~340 {} efcount:b2v_inst1|data[5]~341 {} DATA[5] {} } { 0.000ns 0.000ns 7.054ns 1.242ns 1.521ns 2.647ns } { 0.000ns 1.469ns 0.292ns 0.590ns 0.590ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "efcount:b2v_inst1\|bzq\[0\] SPUL BCLK -6.523 ns register " "Info: th for register \"efcount:b2v_inst1\|bzq\[0\]\" (data pin = \"SPUL\", clock pin = \"BCLK\") is -6.523 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BCLK destination 3.246 ns + Longest register " "Info: + Longest clock path from clock \"BCLK\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BCLK 1 CLK PIN_H1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 32; CLK Node = 'BCLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns efcount:b2v_inst1\|bzq\[0\] 2 REG LC_X10_Y16_N1 5 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X10_Y16_N1; Fanout = 5; REG Node = 'efcount:b2v_inst1\|bzq\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.784 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns SPUL 1 PIN PIN_M5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_M5; Fanout = 1; PIN Node = 'SPUL'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPUL } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.315 ns) + CELL(0.114 ns) 7.904 ns efcount:b2v_inst1\|bena~23 2 COMB LC_X8_Y13_N4 32 " "Info: 2: + IC(6.315 ns) + CELL(0.114 ns) = 7.904 ns; Loc. = LC_X8_Y13_N4; Fanout = 32; COMB Node = 'efcount:b2v_inst1\|bena~23'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.429 ns" { SPUL efcount:b2v_inst1|bena~23 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.571 ns) + CELL(0.309 ns) 9.784 ns efcount:b2v_inst1\|bzq\[0\] 3 REG LC_X10_Y16_N1 5 " "Info: 3: + IC(1.571 ns) + CELL(0.309 ns) = 9.784 ns; Loc. = LC_X10_Y16_N1; Fanout = 5; REG Node = 'efcount:b2v_inst1\|bzq\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.898 ns ( 19.40 % ) " "Info: Total cell delay = 1.898 ns ( 19.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.886 ns ( 80.60 % ) " "Info: Total interconnect delay = 7.886 ns ( 80.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "9.784 ns" { SPUL efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "9.784 ns" { SPUL {} SPUL~out0 {} efcount:b2v_inst1|bena~23 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 6.315ns 1.571ns } { 0.000ns 1.475ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "9.784 ns" { SPUL efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "9.784 ns" { SPUL {} SPUL~out0 {} efcount:b2v_inst1|bena~23 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 6.315ns 1.571ns } { 0.000ns 1.475ns 0.114ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 25 01:12:07 2009 " "Info: Processing ended: Sat Apr 25 01:12:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}