prev_cmp_efcount.tan.qmsg

完整的等精度频率相位计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "efcount:b2v_inst1\|ma " "Info: Detected gated clock \"efcount:b2v_inst1\|ma\" as buffer" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 19 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "efcount:b2v_inst1\|ma" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "efcount:b2v_inst1\|q1 " "Info: Detected ripple clock \"efcount:b2v_inst1\|q1\" as buffer" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 20 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "efcount:b2v_inst1\|q1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "efcount:b2v_inst1\|clk2 " "Info: Detected gated clock \"efcount:b2v_inst1\|clk2\" as buffer" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 19 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "efcount:b2v_inst1\|clk2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "epd:b2v_inst\|SYNTHESIZED_WIRE_14 " "Info: Detected ripple clock \"epd:b2v_inst\|SYNTHESIZED_WIRE_14\" as buffer" {  } { { "epd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/epd.vhd" 85 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "epd:b2v_inst\|SYNTHESIZED_WIRE_14" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "BCLK register register efcount:b2v_inst1\|bzq\[0\] efcount:b2v_inst1\|bzq\[31\] 275.03 MHz Internal " "Info: Clock \"BCLK\" Internal fmax is restricted to 275.03 MHz between source register \"efcount:b2v_inst1\|bzq\[0\]\" and destination register \"efcount:b2v_inst1\|bzq\[31\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.289 ns + Longest register register " "Info: + Longest register to register delay is 3.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns efcount:b2v_inst1\|bzq\[0\] 1 REG LC_X10_Y16_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y16_N1; Fanout = 5; REG Node = 'efcount:b2v_inst1\|bzq\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.575 ns) 1.128 ns efcount:b2v_inst1\|bzq\[1\]~1118COUT1 2 COMB LC_X10_Y16_N5 2 " "Info: 2: + IC(0.553 ns) + CELL(0.575 ns) = 1.128 ns; Loc. = LC_X10_Y16_N5; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|bzq\[1\]~1118COUT1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.128 ns" { efcount:b2v_inst1|bzq[0] efcount:b2v_inst1|bzq[1]~1118COUT1 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.208 ns efcount:b2v_inst1\|bzq\[2\]~1126COUT1 3 COMB LC_X10_Y16_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.208 ns; Loc. = LC_X10_Y16_N6; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|bzq\[2\]~1126COUT1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { efcount:b2v_inst1|bzq[1]~1118COUT1 efcount:b2v_inst1|bzq[2]~1126COUT1 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.288 ns efcount:b2v_inst1\|bzq\[3\]~1134COUT1 4 COMB LC_X10_Y16_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.288 ns; Loc. = LC_X10_Y16_N7; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|bzq\[3\]~1134COUT1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { efcount:b2v_inst1|bzq[2]~1126COUT1 efcount:b2v_inst1|bzq[3]~1134COUT1 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.368 ns efcount:b2v_inst1\|bzq\[4\]~1142COUT1 5 COMB LC_X10_Y16_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.368 ns; Loc. = LC_X10_Y16_N8; Fanout = 2; COMB Node = 'efcount:b2v_inst1\|bzq\[4\]~1142COUT1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { efcount:b2v_inst1|bzq[3]~1134COUT1 efcount:b2v_inst1|bzq[4]~1142COUT1 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.626 ns efcount:b2v_inst1\|bzq\[5\]~1150 6 COMB LC_X10_Y16_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.626 ns; Loc. = LC_X10_Y16_N9; Fanout = 6; COMB Node = 'efcount:b2v_inst1\|bzq\[5\]~1150'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { efcount:b2v_inst1|bzq[4]~1142COUT1 efcount:b2v_inst1|bzq[5]~1150 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.762 ns efcount:b2v_inst1\|bzq\[10\]~1124 7 COMB LC_X10_Y15_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.762 ns; Loc. = LC_X10_Y15_N4; Fanout = 6; COMB Node = 'efcount:b2v_inst1\|bzq\[10\]~1124'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { efcount:b2v_inst1|bzq[5]~1150 efcount:b2v_inst1|bzq[10]~1124 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.970 ns efcount:b2v_inst1\|bzq\[15\]~1164 8 COMB LC_X10_Y15_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 1.970 ns; Loc. = LC_X10_Y15_N9; Fanout = 6; COMB Node = 'efcount:b2v_inst1\|bzq\[15\]~1164'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { efcount:b2v_inst1|bzq[10]~1124 efcount:b2v_inst1|bzq[15]~1164 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.106 ns efcount:b2v_inst1\|bzq\[20\]~1138 9 COMB LC_X10_Y14_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.106 ns; Loc. = LC_X10_Y14_N4; Fanout = 6; COMB Node = 'efcount:b2v_inst1\|bzq\[20\]~1138'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { efcount:b2v_inst1|bzq[15]~1164 efcount:b2v_inst1|bzq[20]~1138 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.314 ns efcount:b2v_inst1\|bzq\[25\]~1120 10 COMB LC_X10_Y14_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.314 ns; Loc. = LC_X10_Y14_N9; Fanout = 6; COMB Node = 'efcount:b2v_inst1\|bzq\[25\]~1120'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { efcount:b2v_inst1|bzq[20]~1138 efcount:b2v_inst1|bzq[25]~1120 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.450 ns efcount:b2v_inst1\|bzq\[30\]~1160 11 COMB LC_X10_Y13_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.450 ns; Loc. = LC_X10_Y13_N4; Fanout = 1; COMB Node = 'efcount:b2v_inst1\|bzq\[30\]~1160'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { efcount:b2v_inst1|bzq[25]~1120 efcount:b2v_inst1|bzq[30]~1160 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.289 ns efcount:b2v_inst1\|bzq\[31\] 12 REG LC_X10_Y13_N5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.839 ns) = 3.289 ns; Loc. = LC_X10_Y13_N5; Fanout = 2; REG Node = 'efcount:b2v_inst1\|bzq\[31\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { efcount:b2v_inst1|bzq[30]~1160 efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 83.19 % ) " "Info: Total cell delay = 2.736 ns ( 83.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 16.81 % ) " "Info: Total interconnect delay = 0.553 ns ( 16.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.289 ns" { efcount:b2v_inst1|bzq[0] efcount:b2v_inst1|bzq[1]~1118COUT1 efcount:b2v_inst1|bzq[2]~1126COUT1 efcount:b2v_inst1|bzq[3]~1134COUT1 efcount:b2v_inst1|bzq[4]~1142COUT1 efcount:b2v_inst1|bzq[5]~1150 efcount:b2v_inst1|bzq[10]~1124 efcount:b2v_inst1|bzq[15]~1164 efcount:b2v_inst1|bzq[20]~1138 efcount:b2v_inst1|bzq[25]~1120 efcount:b2v_inst1|bzq[30]~1160 efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.289 ns" { efcount:b2v_inst1|bzq[0] {} efcount:b2v_inst1|bzq[1]~1118COUT1 {} efcount:b2v_inst1|bzq[2]~1126COUT1 {} efcount:b2v_inst1|bzq[3]~1134COUT1 {} efcount:b2v_inst1|bzq[4]~1142COUT1 {} efcount:b2v_inst1|bzq[5]~1150 {} efcount:b2v_inst1|bzq[10]~1124 {} efcount:b2v_inst1|bzq[15]~1164 {} efcount:b2v_inst1|bzq[20]~1138 {} efcount:b2v_inst1|bzq[25]~1120 {} efcount:b2v_inst1|bzq[30]~1160 {} efcount:b2v_inst1|bzq[31] {} } { 0.000ns 0.553ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.035 ns - Smallest " "Info: - Smallest clock skew is -0.035 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BCLK destination 3.211 ns + Shortest register " "Info: + Shortest clock path from clock \"BCLK\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BCLK 1 CLK PIN_H1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 32; CLK Node = 'BCLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns efcount:b2v_inst1\|bzq\[31\] 2 REG LC_X10_Y13_N5 2 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X10_Y13_N5; Fanout = 2; REG Node = 'efcount:b2v_inst1\|bzq\[31\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { BCLK efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.211 ns" { BCLK efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.211 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[31] {} } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BCLK source 3.246 ns - Longest register " "Info: - Longest clock path from clock \"BCLK\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BCLK 1 CLK PIN_H1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 32; CLK Node = 'BCLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns efcount:b2v_inst1\|bzq\[0\] 2 REG LC_X10_Y16_N1 5 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X10_Y16_N1; Fanout = 5; REG Node = 'efcount:b2v_inst1\|bzq\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.211 ns" { BCLK efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.211 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[31] {} } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.289 ns" { efcount:b2v_inst1|bzq[0] efcount:b2v_inst1|bzq[1]~1118COUT1 efcount:b2v_inst1|bzq[2]~1126COUT1 efcount:b2v_inst1|bzq[3]~1134COUT1 efcount:b2v_inst1|bzq[4]~1142COUT1 efcount:b2v_inst1|bzq[5]~1150 efcount:b2v_inst1|bzq[10]~1124 efcount:b2v_inst1|bzq[15]~1164 efcount:b2v_inst1|bzq[20]~1138 efcount:b2v_inst1|bzq[25]~1120 efcount:b2v_inst1|bzq[30]~1160 efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.289 ns" { efcount:b2v_inst1|bzq[0] {} efcount:b2v_inst1|bzq[1]~1118COUT1 {} efcount:b2v_inst1|bzq[2]~1126COUT1 {} efcount:b2v_inst1|bzq[3]~1134COUT1 {} efcount:b2v_inst1|bzq[4]~1142COUT1 {} efcount:b2v_inst1|bzq[5]~1150 {} efcount:b2v_inst1|bzq[10]~1124 {} efcount:b2v_inst1|bzq[15]~1164 {} efcount:b2v_inst1|bzq[20]~1138 {} efcount:b2v_inst1|bzq[25]~1120 {} efcount:b2v_inst1|bzq[30]~1160 {} efcount:b2v_inst1|bzq[31] {} } { 0.000ns 0.553ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.211 ns" { BCLK efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.211 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[31] {} } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { BCLK efcount:b2v_inst1|bzq[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[0] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { efcount:b2v_inst1|bzq[31] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { efcount:b2v_inst1|bzq[31] {} } {  } {  } "" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CL " "Info: No valid register-to-register data paths exist for clock \"CL\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "efcount:b2v_inst1\|bzq\[26\] SPUL BCLK 7.655 ns register " "Info: tsu for register \"efcount:b2v_inst1\|bzq\[26\]\" (data pin = \"SPUL\", clock pin = \"BCLK\") is 7.655 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.829 ns + Longest pin register " "Info: + Longest pin to register delay is 10.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns SPUL 1 PIN PIN_M5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_M5; Fanout = 1; PIN Node = 'SPUL'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPUL } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.315 ns) + CELL(0.114 ns) 7.904 ns efcount:b2v_inst1\|bena~23 2 COMB LC_X8_Y13_N4 32 " "Info: 2: + IC(6.315 ns) + CELL(0.114 ns) = 7.904 ns; Loc. = LC_X8_Y13_N4; Fanout = 32; COMB Node = 'efcount:b2v_inst1\|bena~23'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.429 ns" { SPUL efcount:b2v_inst1|bena~23 } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.058 ns) + CELL(0.867 ns) 10.829 ns efcount:b2v_inst1\|bzq\[26\] 3 REG LC_X10_Y13_N0 4 " "Info: 3: + IC(2.058 ns) + CELL(0.867 ns) = 10.829 ns; Loc. = LC_X10_Y13_N0; Fanout = 4; REG Node = 'efcount:b2v_inst1\|bzq\[26\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.456 ns ( 22.68 % ) " "Info: Total cell delay = 2.456 ns ( 22.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.373 ns ( 77.32 % ) " "Info: Total interconnect delay = 8.373 ns ( 77.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "10.829 ns" { SPUL efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "10.829 ns" { SPUL {} SPUL~out0 {} efcount:b2v_inst1|bena~23 {} efcount:b2v_inst1|bzq[26] {} } { 0.000ns 0.000ns 6.315ns 2.058ns } { 0.000ns 1.475ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BCLK destination 3.211 ns - Shortest register " "Info: - Shortest clock path from clock \"BCLK\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BCLK 1 CLK PIN_H1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 32; CLK Node = 'BCLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCLK } "NODE_NAME" } } { "efepd.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efepd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns efcount:b2v_inst1\|bzq\[26\] 2 REG LC_X10_Y13_N0 4 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X10_Y13_N0; Fanout = 4; REG Node = 'efcount:b2v_inst1\|bzq\[26\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { BCLK efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "efcount.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/efcount/efcount.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.211 ns" { BCLK efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.211 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[26] {} } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "10.829 ns" { SPUL efcount:b2v_inst1|bena~23 efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "10.829 ns" { SPUL {} SPUL~out0 {} efcount:b2v_inst1|bena~23 {} efcount:b2v_inst1|bzq[26] {} } { 0.000ns 0.000ns 6.315ns 2.058ns } { 0.000ns 1.475ns 0.114ns 0.867ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "3.211 ns" { BCLK efcount:b2v_inst1|bzq[26] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "3.211 ns" { BCLK {} BCLK~out0 {} efcount:b2v_inst1|bzq[26] {} } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}