mux.v

基于verilog的时钟定时器的硬件实现

module Mux(ALARM, ALARM_HRS, ALARM_MIN, ALARM_AM_PM, TIME_HRS, TIME_MIN, TIME_AM_PM, AM_PM_SHOW, OUT_SHOW);
input ALARM, ALARM_HRS, ALARM_MIN, ALARM_AM_PM, TIME_HRS, TIME_MIN, TIME_AM_PM;
output AM_PM_SHOW, OUT_SHOW;
wire ALARM;
wire [3:0] ALARM_HRS, TIME_HRS;
wire [5:0] ALARM_MIN, TIME_MIN;
wire ALARM_AM_PM, TIME_AM_PM;
reg AM_PM_SHOW;
reg [9:0] OUT_SHOW;

always@(*)
     begin
         if(ALARM)
             begin
                OUT_SHOW= {ALARM_HRS, ALARM_MIN};
                AM_PM_SHOW= ALARM_AM_PM;
             end
         else 
             begin
                OUT_SHOW= {TIME_HRS, TIME_MIN};
                AM_PM_SHOW= TIME_AM_PM;    
             end
     end
     
endmodule