alarm_counter.v

基于verilog的时钟定时器的硬件实现

module ALARM_COUNTER(CLK, HRS, MINS, ALARM, HRS_OUT, MINS_OUT, AM_PM, RESET);
input CLK, HRS, MINS, ALARM, RESET;
output HRS_OUT, MINS_OUT, AM_PM;
wire CLK, HRS, MINS, ALARM, RESET;
reg [3:0] HRS_OUT;
reg [5:0] MINS_OUT;
reg AM_PM;
reg MINS_CARRY, HRS_CARRY;

parameter  AM = 0;
parameter  PM = 1;
    
always@(posedge CLK)
   begin
     if(RESET==1) begin
        HRS_OUT<= 0;
        MINS_OUT<= 0;
        AM_PM<= AM;
      end
      else begin
      if(ALARM)
          begin
             if(HRS)
                 if(HRS_CARRY)
                     begin 
                         HRS_OUT<= 0;
                         AM_PM<= ~AM_PM;
                     end
                  else
                         HRS_OUT<= HRS_OUT+ 1;
             if(MINS)
                 if(MINS_CARRY)
                     MINS_OUT<= 0;
                  else
                     MINS_OUT<= MINS_OUT+ 1;
          end
      end
    end
    
always@(posedge CLK)
   begin
      if(MINS_OUT== 58)
          MINS_CARRY<= 1;
      else
          MINS_CARRY<= 0;
      if(HRS_OUT== 10)
          HRS_CARRY<= 1;
      else
          HRS_CARRY<= 0;
   end
   
endmodule