time_counter.v

基于verilog的时钟定时器的硬件实现

module TIME_COUNTER(CLK, HRS, MINS, SECS, HRS_OUT, MINS_OUT, AM_PM, RESET);
input CLK, HRS, MINS, SECS, RESET;
output HRS_OUT, MINS_OUT, AM_PM;
wire CLK, HRS, MINS, SECS, RESET;
reg [3:0] HRS_OUT;
reg [5:0] MINS_OUT, SECS_OUT;
reg AM_PM;
reg SECS_CARRY, MINS_CARRY, HRS_CARRY;
parameter AM = 0;
parameter PM = 1;

   
always@(posedge CLK)
   begin 
     if(RESET==1)
        begin
           HRS_OUT<= 0;
           MINS_OUT<= 0;
           SECS_OUT<= 0;
           AM_PM<= AM;
        end
      else begin
        if(SECS)
           begin 
            if(SECS_CARRY)
              begin
                 SECS_OUT<= 0;
                 MINS_OUT<= MINS_OUT + 1;
              end
            else 
                 SECS_OUT<= SECS_OUT+ 1;
            if(MINS_CARRY)
              begin
                 MINS_OUT<= 0;
                 HRS_OUT<= HRS_OUT+1;
              end
            
            if(HRS_CARRY)
              begin
                 HRS_OUT<= 0;
                 AM_PM<= ~AM_PM;
              end
          
          end
       else
          begin
             if(HRS)
               if(HRS_CARRY)
                  begin
                    HRS_OUT<= 0;
                    AM_PM<= ~AM_PM;
                  end
               else
                    HRS_OUT<= HRS_OUT+ 1;
             if(MINS)
               if(MINS_CARRY)
                  MINS_OUT<= 0;
               else
                  MINS_OUT<= MINS_OUT+ 1;
          end
      end
   end
   
always@(posedge CLK)
   begin
      if(SECS)
        begin
            if(SECS_OUT== 58)
                SECS_CARRY<= 1;
            else
                SECS_CARRY<= 0;
            if(SECS_OUT== 58 && MINS_OUT== 59)
                MINS_CARRY<= 1;
            else
                MINS_CARRY<= 0;
            if(SECS_OUT==58 && MINS_OUT==59 && HRS_OUT==11)
                HRS_CARRY<= 1;
            else
                HRS_CARRY<= 0;
        end
      if(MINS)
           if(MINS_OUT==59)
                MINS_CARRY<= 1;
           else
                MINS_CARRY<= 0;
        
      if(HRS)
           if(HRS_OUT== 11)
                HRS_CARRY<= 1;
           else
                HRS_CARRY<= 0;
    end
    
endmodule