_primary.vhd

来自「简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity comp is
    port(
        a1              : in     vl_logic_vector(3 downto 0);
        a2              : in     vl_logic_vector(3 downto 0);
        min             : out    vl_logic_vector(3 downto 0);
        max             : out    vl_logic_vector(3 downto 0)
    );
end comp;