_primary.vhd

来自「简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity sfifo is
    port(
        clk             : in     vl_logic;
        wen             : in     vl_logic;
        wptr            : in     vl_logic_vector(3 downto 0);
        rptr            : in     vl_logic_vector(3 downto 0);
        din             : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(7 downto 0)
    );
end sfifo;